intel PCI ops: Remove explicit PCI MMCONF access

MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17529
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 17 insertions, 17 deletions

diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c
index b81030d3d3..6a8d6f1f06 100644
--- a/src/southbridge/intel/fsp_bd82x6x/finalize.c
+++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c
@@ -52,8 +52,8 @@ void intel_pch_finalize_smm(void)
 
 	/* R/WO registers */
 	RCBA32(0x21a4) = RCBA32(0x21a4);
-	pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
-		    pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+	pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
+		    pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
 
 	/* Indicate finalize step with post code */
 	outb(POST_OS_BOOT, 0x80);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index a951f9f191..a634134084 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -496,14 +496,14 @@ static void intel_me7_finalize_smm(void)
 	u32 reg32;
 
 	mei_base_address = (u32 *)
-		(pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
+		(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
 
 	/* S3 path will have hidden this device already */
 	if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
 		return;
 
 	/* Make sure ME is in a mode that expects EOP */
-	reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+	reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
 	memcpy(&hfs, &reg32, sizeof(u32));
 
 	/* Abort and leave device alone if not normal mode */
@@ -516,10 +516,10 @@ static void intel_me7_finalize_smm(void)
 	mkhi_end_of_post();
 
 	/* Make sure IO is disabled */
-	reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+	reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
 	reg32 &= ~(PCI_COMMAND_MASTER |
 		   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-	pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+	pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
 
 	/* Hide the PCI device */
 	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@@ -527,7 +527,7 @@ static void intel_me7_finalize_smm(void)
 
 void intel_me_finalize_smm(void)
 {
-	u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
+	u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
 	switch (did) {
 	case 0x1c3a8086:
 		intel_me7_finalize_smm();
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index 0d3a01e7c7..4001fb9575 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -489,14 +489,14 @@ void intel_me8_finalize_smm(void)
 	u32 reg32;
 
 	mei_base_address = (u32 *)
-		(pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
+		(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
 
 	/* S3 path will have hidden this device already */
 	if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
 		return;
 
 	/* Make sure ME is in a mode that expects EOP */
-	reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+	reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
 	memcpy(&hfs, &reg32, sizeof(u32));
 
 	/* Abort and leave device alone if not normal mode */
@@ -509,10 +509,10 @@ void intel_me8_finalize_smm(void)
 	mkhi_end_of_post();
 
 	/* Make sure IO is disabled */
-	reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+	reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
 	reg32 &= ~(PCI_COMMAND_MASTER |
 		   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-	pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+	pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
 
 	/* Hide the PCI device */
 	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 01ace5970f..19337e9d14 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -279,7 +279,7 @@ static void southbridge_gate_memory_reset(void)
 	u32 reg32;
 	u16 gpiobase;
 
-	gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
+	gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
 	if (!gpiobase)
 		return;
 
@@ -361,13 +361,13 @@ static void southbridge_smi_sleep(void)
 		/* Always set the flag in case CMOS was changed on runtime. For
 		 * "KEEP", switch to "OFF" - KEEP is software emulated
 		 */
-		reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+		reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
 		if (s5pwr == MAINBOARD_POWER_ON) {
 			reg8 &= ~1;
 		} else {
 			reg8 |= 1;
 		}
-		pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+		pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
 
 		/* also iterates over all bridges on bus 0 */
 		busmaster_disable_on_bus(0);
@@ -588,7 +588,7 @@ static void southbridge_smi_tco(void)
 	if (tco_sts & (1 << 8)) { // BIOSWR
 		u8 bios_cntl;
 
-		bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+		bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
 
 		if (bios_cntl & 1) {
 			/* BWE is RW, so the SMI was caused by a
@@ -602,7 +602,7 @@ static void southbridge_smi_tco(void)
 			 * box.
 			 */
 			printk(BIOS_DEBUG, "Switching back to RO\n");
-			pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+			pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
 		} /* No else for now? */
 	} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
 		/* Handle TCO timeout */
@@ -729,7 +729,7 @@ void southbridge_smi_handler(void)
 	u32 smi_sts;
 
 	/* Update global variable pmbase */
-	pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+	pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
 
 	/* We need to clear the SMI status registers, or we won't see what's
 	 * happening in the following calls.