diff options
| author | Martin Roth <gaumless@gmail.com> | 2015-06-20 16:17:12 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2015-06-23 22:48:45 +0200 |
| commit | 59aa2b191b5b510e6a0567f6d2be5d1b97195c95 (patch) | |
| tree | 2efb596e30a342423b7f18ff4984dcc0e207511b /src/southbridge/intel/fsp_bd82x6x | |
| parent | 6ab0fd0a9455d35dde5c359845d35bb337b7666e (diff) | |
southbridge/intel: Create common IFD Kconfig and Makefile
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC.
This is the start of creating a common interface for all of them.
This also allows us to reduce the chipset dependencies for CBFS_SIZE.
Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10613
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/Kconfig | 33 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 28 |
2 files changed, 3 insertions, 58 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index f60cbb1e64..fc2b6b36a2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -33,6 +33,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select HAVE_INTEL_FIRMWARE + select USES_INTEL_ME config EHCI_BAR hex @@ -53,35 +55,4 @@ config HPET_MIN_TICKS hex default 0x80 -if HAVE_FSP_BIN - -config INCLUDE_ME - bool - default n - help - Include the me.bin and descriptor.bin for Intel PCH. - This is usually required for the PCH. - -config ME_PATH - string - depends on INCLUDE_ME - help - The path of the ME and Descriptor files. - -config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" - default n - depends on INCLUDE_ME - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. - -endif # HAVE_FSP_BIN - endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 44144a0302..d96e641670 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -20,12 +20,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -ifeq ($(CONFIG_INCLUDE_ME),y) -INTERMEDIATE+=bd82x6x_add_me -endif +subdirs-y += ../common/firmware ramstage-y += pch.c ramstage-y += azalia.c @@ -51,27 +46,6 @@ smm-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c romstage-y += early_spi.c -bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/me.bin \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -PHONY += bd82x6x_add_me - CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x endif |