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authorStefan Reinauer <reinauer@chromium.org>2013-08-01 13:31:44 -0700
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-05 22:21:49 +0100
commit3a6550d989460f9449136814a8b1f6b051a6382d (patch)
treed60bdfd55ddcc5e45042c987d5216d9212784f60 /src/southbridge/intel/fsp_bd82x6x
parent83405a1241f4b8f516f687bd00f8ea981f7c7d87 (diff)
timestamps: Switch from tsc_t to uint64_t
Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x')
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/bootblock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
index 61ff3018c1..9b3e97aa34 100644
--- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c
+++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
@@ -34,7 +34,7 @@ static void store_initial_timestamp(void)
* only storing the low nibble of the high dword of the tsc. Even this
* is probably 0 by the time we get here, so storing 64 bits is overkill.S
*/
- pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28);
+ pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28);
}
/*