diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-13 13:05:48 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-22 07:20:14 +0000 |
| commit | 4ccb23fe27bc9fa45b6db8a7b4ec519a3c25674b (patch) | |
| tree | 9bc7035687e08371ca5216ddaaf219584a131846 /src/southbridge/intel/fsp_bd82x6x/pch.c | |
| parent | b7482219e8078ae7ac973b20e5f6aac6d05b7f48 (diff) | |
sb/intel/fsp_bd82x6x: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I499414c067b06fa94b53832894e804118f7c3e80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/pch.c')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/pch.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.c b/src/southbridge/intel/fsp_bd82x6x/pch.c index 3ad45fc585..1613be85b2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.c +++ b/src/southbridge/intel/fsp_bd82x6x/pch.c @@ -188,9 +188,9 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) } /* Check if any port in set X to X+3 is enabled */ -static int pch_pcie_check_set_enabled(device_t dev) +static int pch_pcie_check_set_enabled(struct device *dev) { - device_t port; + struct device *port; int port_func; int dev_func = PCI_FUNC(dev->path.pci.devfn); @@ -237,7 +237,7 @@ static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_devicetree_update(void) { - device_t dev; + struct device *dev; /* Update the function numbers in the static devicetree */ for (dev = all_devices; dev; dev = dev->next) { @@ -266,7 +266,7 @@ static void pch_pcie_devicetree_update(void) } /* Special handling for PCIe Root Port devices */ -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { struct southbridge_intel_fsp_bd82x6x_config *config = dev->chip_info; u32 reg32; @@ -373,7 +373,7 @@ static void pch_pcie_enable(device_t dev) } } -void pch_enable(device_t dev) +void pch_enable(struct device *dev) { u32 reg32; |