Add Intel FSP bd82x6x southbridge support

Add support for the bd82x6x using the Intel FSP.
The FSP is different enough to warrant its own source files
for now. The mrc/system agent chromebook solution does much more
southbridge initialization and configuration than the FSP version.
It may be combined in the future.

Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 660 insertions, 0 deletions

diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
new file mode 100644
index 0000000000..2633a49836
--- /dev/null
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -0,0 +1,660 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <pc80/i8259.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <elog.h>
+#include "pch.h"
+
+#define NMI_OFF	0
+
+#define ENABLE_ACPI_MODE_IN_COREBOOT	0
+#define TEST_SMM_FLASH_LOCKDOWN		0
+
+typedef struct southbridge_intel_fsp_bd82x6x_config config_t;
+
+static void pch_enable_apic(struct device *dev)
+{
+	int i;
+	u32 reg32;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+	/* Enable ACPI I/O and power management.
+	 * Set SCI IRQ to IRQ9
+	 */
+	pci_write_config8(dev, ACPI_CNTL, 0x80);
+
+	*ioapic_index = 0;
+	*ioapic_data = (1 << 25);
+
+	/* affirm full set of redirection table entries ("write once") */
+	*ioapic_index = 1;
+	reg32 = *ioapic_data;
+	*ioapic_index = 1;
+	*ioapic_data = reg32;
+
+	*ioapic_index = 0;
+	reg32 = *ioapic_data;
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+	if (reg32 != (1 << 25))
+		die("APIC Error\n");
+
+	printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
+	for (i=0; i<3; i++) {
+		*ioapic_index = i;
+		printk(BIOS_SPEW, "  reg 0x%04x:", i);
+		reg32 = *ioapic_data;
+		printk(BIOS_SPEW, " 0x%08x\n", reg32);
+	}
+
+	*ioapic_index = 3; /* Select Boot Configuration register. */
+	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+}
+
+static void pch_enable_serial_irqs(struct device *dev)
+{
+	/* Set packet length and toggle silent mode bit for one frame. */
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
+#endif
+}
+
+/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+
+static void pch_pirq_init(device_t dev)
+{
+	device_t irq_dev;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+	pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+	pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+	pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+
+	pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+	pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+	pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+	pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+
+	/* Eric Biederman once said we should let the OS do this.
+	 * I am not so sure anymore he was right.
+	 */
+
+	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+		u8 int_pin=0, int_line=0;
+
+		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+			continue;
+
+		int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+
+		switch (int_pin) {
+		case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+		case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+		case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+		case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+		}
+
+		if (!int_line)
+			continue;
+
+		pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+	}
+}
+
+static void pch_gpi_routing(device_t dev)
+{
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+	u32 reg32 = 0;
+
+	/* An array would be much nicer here, or some
+	 * other method of doing this.
+	 */
+	reg32 |= (config->gpi0_routing & 0x03) << 0;
+	reg32 |= (config->gpi1_routing & 0x03) << 2;
+	reg32 |= (config->gpi2_routing & 0x03) << 4;
+	reg32 |= (config->gpi3_routing & 0x03) << 6;
+	reg32 |= (config->gpi4_routing & 0x03) << 8;
+	reg32 |= (config->gpi5_routing & 0x03) << 10;
+	reg32 |= (config->gpi6_routing & 0x03) << 12;
+	reg32 |= (config->gpi7_routing & 0x03) << 14;
+	reg32 |= (config->gpi8_routing & 0x03) << 16;
+	reg32 |= (config->gpi9_routing & 0x03) << 18;
+	reg32 |= (config->gpi10_routing & 0x03) << 20;
+	reg32 |= (config->gpi11_routing & 0x03) << 22;
+	reg32 |= (config->gpi12_routing & 0x03) << 24;
+	reg32 |= (config->gpi13_routing & 0x03) << 26;
+	reg32 |= (config->gpi14_routing & 0x03) << 28;
+	reg32 |= (config->gpi15_routing & 0x03) << 30;
+
+	pci_write_config32(dev, 0xb8, reg32);
+}
+
+static void pch_power_options(device_t dev)
+{
+	u8 reg8;
+	u16 reg16, pmbase;
+	u32 reg32;
+	const char *state;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int nmi_option;
+
+	/* Which state do we want to goto after g3 (power restored)?
+	 * 0 == S0 Full On
+	 * 1 == S5 Soft Off
+	 *
+	 * If the option is not existent (Laptops), use Kconfig setting.
+	 */
+	get_option(&pwr_on, "power_on_after_fail");
+
+	reg16 = pci_read_config16(dev, GEN_PMCON_3);
+	reg16 &= 0xfffe;
+	switch (pwr_on) {
+	case MAINBOARD_POWER_OFF:
+		reg16 |= 1;
+		state = "off";
+		break;
+	case MAINBOARD_POWER_ON:
+		reg16 &= ~1;
+		state = "on";
+		break;
+	case MAINBOARD_POWER_KEEP:
+		reg16 &= ~1;
+		state = "state keep";
+		break;
+	default:
+		state = "undefined";
+	}
+
+	reg16 &= ~(3 << 4);	/* SLP_S4# Assertion Stretch 4s */
+	reg16 |= (1 << 3);	/* SLP_S4# Assertion Stretch Enable */
+
+	reg16 &= ~(1 << 10);
+	reg16 |= (1 << 11);	/* SLP_S3# Min Assertion Width 50ms */
+
+	reg16 |= (1 << 12);	/* Disable SLP stretch after SUS well */
+
+	pci_write_config16(dev, GEN_PMCON_3, reg16);
+	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
+
+	/* Set up NMI on errors. */
+	reg8 = inb(0x61);
+	reg8 &= 0x0f;		/* Higher Nibble must be 0 */
+	reg8 &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	// reg8 &= ~(1 << 2);	/* PCI SERR# Enable */
+	reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+	outb(reg8, 0x61);
+
+	reg8 = inb(0x70);
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		printk(BIOS_INFO, "NMI sources enabled.\n");
+		reg8 &= ~(1 << 7);	/* Set NMI. */
+	} else {
+		printk(BIOS_INFO, "NMI sources disabled.\n");
+		reg8 |= ( 1 << 7);	/* Can't mask NMI from PCI-E and NMI_NOW */
+	}
+	outb(reg8, 0x70);
+
+	/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
+	reg16 = pci_read_config16(dev, GEN_PMCON_1);
+	reg16 &= ~(3 << 0);	// SMI# rate 1 minute
+	reg16 &= ~(1 << 10);	// Disable BIOS_PCI_EXP_EN for native PME
+#if DEBUG_PERIODIC_SMIS
+	/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
+	 * periodic SMIs.
+	 */
+	reg16 |= (3 << 0); // Periodic SMI every 8s
+#endif
+	pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+	// Set the board's GPI routing.
+	pch_gpi_routing(dev);
+
+	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+	outl(config->gpe0_en, pmbase + GPE0_EN);
+	outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
+
+	/* Set up power management block and determine sleep mode */
+	reg32 = inl(pmbase + 0x04); // PM1_CNT
+	reg32 &= ~(7 << 10);	// SLP_TYP
+	reg32 |= (1 << 0);	// SCI_EN
+	outl(reg32, pmbase + 0x04);
+
+	/* Clear magic status bits to prevent unexpected wake */
+	reg32 = RCBA32(0x3310);
+	reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
+	RCBA32(0x3310) = reg32;
+}
+
+static void pch_rtc_init(struct device *dev)
+{
+	u8 reg8;
+	int rtc_failed;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = reg8 & RTC_BATTERY_DEAD;
+	if (rtc_failed) {
+		reg8 &= ~RTC_BATTERY_DEAD;
+		pci_write_config8(dev, GEN_PMCON_3, reg8);
+#if CONFIG_ELOG
+		elog_add_event(ELOG_TYPE_RTC_RESET);
+#endif
+	}
+	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
+
+	rtc_init(rtc_failed);
+}
+
+/* CougarPoint PCH Power Management init */
+static void cpt_pm_init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "CougarPoint PM init\n");
+	pci_write_config8(dev, 0xa9, 0x47);
+	RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0));
+	RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
+	RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
+	RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
+	RCBA32(0x2304) = 0xc0388400;
+	RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
+	RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
+	RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
+	RCBA32(0x3318) = 0x050f0000;
+	RCBA32(0x3324) = 0x04000000;
+	RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
+	RCBA32_AND_OR(0x3344, ~0UL, (1 << 1));
+	RCBA32(0x3360) = 0x0001c000;
+	RCBA32(0x3368) = 0x00061100;
+	RCBA32(0x3378) = 0x7f8fdfff;
+	RCBA32(0x337c) = 0x000003fc;
+	RCBA32(0x3388) = 0x00001000;
+	RCBA32(0x3390) = 0x0001c000;
+	RCBA32(0x33a0) = 0x00000800;
+	RCBA32(0x33b0) = 0x00001000;
+	RCBA32(0x33c0) = 0x00093900;
+	RCBA32(0x33cc) = 0x24653002;
+	RCBA32(0x33d0) = 0x062108fe;
+	RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
+	RCBA32(0x3a28) = 0x01010000;
+	RCBA32(0x3a2c) = 0x01010404;
+	RCBA32(0x3a80) = 0x01041041;
+	RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
+	RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
+	RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0));  /* SATA 4/5 disabled */
+	RCBA32(0x3a6c) = 0x00000001;
+	RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
+	RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
+	RCBA32(0x33c8) = 0;
+	RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
+}
+
+/* PantherPoint PCH Power Management init */
+static void ppt_pm_init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "PantherPoint PM init\n");
+	pci_write_config8(dev, 0xa9, 0x47);
+	RCBA32_AND_OR(0x2238, ~0UL, (1 << 0));
+	RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
+	RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
+	RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
+	RCBA32(0x2304) = 0xc03b8400;
+	RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
+	RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
+	RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
+	RCBA32(0x3318) = 0x054f0000;
+	RCBA32(0x3324) = 0x04000000;
+	RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
+	RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0));
+	RCBA32(0x3360) = 0x0001c000;
+	RCBA32(0x3368) = 0x00061100;
+	RCBA32(0x3378) = 0x7f8fdfff;
+	RCBA32(0x337c) = 0x000003fd;
+	RCBA32(0x3388) = 0x00001000;
+	RCBA32(0x3390) = 0x0001c000;
+	RCBA32(0x33a0) = 0x00000800;
+	RCBA32(0x33b0) = 0x00001000;
+	RCBA32(0x33c0) = 0x00093900;
+	RCBA32(0x33cc) = 0x24653002;
+	RCBA32(0x33d0) = 0x067388fe;
+	RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
+	RCBA32(0x3a28) = 0x01010000;
+	RCBA32(0x3a2c) = 0x01010404;
+	RCBA32(0x3a80) = 0x01040000;
+	RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
+	RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
+	RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0));  /* SATA 4/5 disabled */
+	RCBA32(0x3a6c) = 0x00000001;
+	RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
+	RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
+	RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0));
+	RCBA32(0x33c8) = 0;
+	RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
+}
+
+static void enable_hpet(void)
+{
+	u32 reg32;
+
+	/* Move HPET to default address 0xfed00000 and enable it */
+	reg32 = RCBA32(HPTC);
+	reg32 |= (1 << 7); // HPET Address Enable
+	reg32 &= ~(3 << 0);
+	RCBA32(HPTC) = reg32;
+}
+
+#if CONFIG_HAVE_SMI_HANDLER
+static void pch_lock_smm(struct device *dev)
+{
+#if TEST_SMM_FLASH_LOCKDOWN
+	u8 reg8;
+#endif
+
+	if (acpi_slp_type != 3) {
+#if ENABLE_ACPI_MODE_IN_COREBOOT
+		printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
+		outb(0xe1, 0xb2); // Enable ACPI mode
+		printk(BIOS_DEBUG, "done.\n");
+#else
+		printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+		outb(0x1e, 0xb2); // Disable ACPI mode
+		printk(BIOS_DEBUG, "done.\n");
+#endif
+	}
+
+	/* Don't allow evil boot loaders, kernels, or
+	 * userspace applications to deceive us:
+	 */
+	smm_lock();
+
+#if TEST_SMM_FLASH_LOCKDOWN
+	/* Now try this: */
+	printk(BIOS_DEBUG, "Locking BIOS to RO... ");
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+	reg8 &= ~(1 << 0);			/* clear BIOSWE */
+	pci_write_config8(dev, 0xdc, reg8);
+	reg8 |= (1 << 1);			/* set BLE */
+	pci_write_config8(dev, 0xdc, reg8);
+	printk(BIOS_DEBUG, "ok.\n");
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+
+	printk(BIOS_DEBUG, "Writing:\n");
+	*(volatile u8 *)0xfff00000 = 0x00;
+	printk(BIOS_DEBUG, "Testing:\n");
+	reg8 |= (1 << 0);			/* set BIOSWE */
+	pci_write_config8(dev, 0xdc, reg8);
+
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+	printk(BIOS_DEBUG, "Done.\n");
+#endif
+}
+#endif
+
+static void pch_disable_smm_only_flashing(struct device *dev)
+{
+	u8 reg8;
+
+	printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	reg8 &= ~(1 << 5);
+	pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void pch_fixups(struct device *dev)
+{
+	u8 gen_pmcon_2;
+
+	/* Indicate DRAM init done for MRC S3 to know it can resume */
+	gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
+	gen_pmcon_2 |= (1 << 7);
+	pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
+
+}
+
+static void pch_decode_init(struct device *dev)
+{
+	config_t *config = dev->chip_info;
+
+	printk(BIOS_DEBUG, "pch_decode_init\n");
+
+	pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
+	pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
+	pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
+	pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
+}
+
+static void lpc_init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "pch: lpc_init\n");
+
+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+	/* IO APIC initialization. */
+	pch_enable_apic(dev);
+
+	pch_enable_serial_irqs(dev);
+
+	/* Setup the PIRQ. */
+	pch_pirq_init(dev);
+
+	/* Setup power options. */
+	pch_power_options(dev);
+
+	/* Initialize power management */
+	switch (pch_silicon_type()) {
+	case PCH_TYPE_CPT: /* CougarPoint */
+		cpt_pm_init(dev);
+		break;
+	case PCH_TYPE_PPT: /* PantherPoint */
+		ppt_pm_init(dev);
+		break;
+	default:
+		printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
+	}
+
+	/* Set the state of the GPIO lines. */
+	//gpio_init(dev);
+
+	/* Initialize the real time clock. */
+	pch_rtc_init(dev);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+	/* Initialize the High Precision Event Timers, if present. */
+	enable_hpet();
+
+	setup_i8259();
+
+	/* The OS should do this? */
+	/* Interrupt 9 should be level triggered (SCI) */
+	i8259_configure_irq_trigger(9, 1);
+
+	pch_disable_smm_only_flashing(dev);
+
+#if CONFIG_HAVE_SMI_HANDLER
+	pch_lock_smm(dev);
+#endif
+
+	pch_fixups(dev);
+}
+
+static void pch_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+	config_t *config = dev->chip_info;
+	u8 io_index = 0;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	/* Set PCH IO decode ranges if required.*/
+	if ((config->gen1_dec & 0xFFFC) > 0x1000) {
+		res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+		res->base = config->gen1_dec & 0xFFFC;
+		res->size = (config->gen1_dec >> 16) & 0xFC;
+		res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+				 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	}
+
+	if ((config->gen2_dec & 0xFFFC) > 0x1000) {
+		res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+		res->base = config->gen2_dec & 0xFFFC;
+		res->size = (config->gen2_dec >> 16) & 0xFC;
+		res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+				 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	}
+
+	if ((config->gen3_dec & 0xFFFC) > 0x1000) {
+		res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+		res->base = config->gen3_dec & 0xFFFC;
+		res->size = (config->gen3_dec >> 16) & 0xFC;
+		res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+				 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	}
+
+	if ((config->gen4_dec & 0xFFFC) > 0x1000) {
+		res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+		res->base = config->gen4_dec & 0xFFFC;
+		res->size = (config->gen4_dec >> 16) & 0xFC;
+		res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
+				 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	}
+}
+
+static void pch_lpc_enable_resources(device_t dev)
+{
+	pch_decode_init(dev);
+	return pci_dev_enable_resources(dev);
+}
+
+static void pch_lpc_enable(device_t dev)
+{
+	pch_enable(dev);
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pch_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pch_lpc_enable_resources,
+	.init			= lpc_init,
+	.enable			= pch_lpc_enable,
+	.scan_bus		= scan_static_bus,
+	.ops_pci		= &pci_ops,
+};
+
+
+/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
+ * Intel C200 Series Chipset
+ */
+
+static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a,
+						 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e,
+						 0x1c4f, 0x1c50, 0x1c52, 0x1c54,
+						 0x1e55, 0x1c56, 0x1e57, 0x1c5c,
+						 0x1e5d, 0x1e5e, 0x1e5f, 0x2310,
+						 0 };
+
+static const struct pci_driver pch_lpc __pci_driver = {
+	.ops	 = &device_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
+
+