diff options
author | Marc Jones <marc.jones@se-eng.com> | 2013-10-29 22:12:32 -0600 |
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committer | Marc Jones <marc.jones@se-eng.com> | 2013-12-04 18:46:35 +0100 |
commit | 73a9b503f00675753f97227d967bb0adddb3ca00 (patch) | |
tree | 03555e9add7c043bf9960f53bde765c33ac10469 /src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl | |
parent | bdafcfa55509d0cf2cbbb686411f569d56d3916c (diff) |
Add Intel FSP bd82x6x southbridge support
Add support for the bd82x6x using the Intel FSP.
The FSP is different enough to warrant its own source files
for now. The mrc/system agent chromebook solution does much more
southbridge initialization and configuration than the FSP version.
It may be combined in the future.
Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl')
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl new file mode 100644 index 0000000000..fedd9c97c6 --- /dev/null +++ b/src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Included in each PCIe Root Port device */ + +OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) +Field (RPCS, AnyAcc, NoLock, Preserve) +{ + Offset (0x4c), // Link Capabilities + , 24, + RPPN, 8, // Root Port Number +} |