diff options
| author | Martin Roth <martinroth@google.com> | 2015-10-11 10:37:02 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-10-22 21:51:01 +0200 |
| commit | bf6b83abe06ff53033e7cd74134972de6791cf26 (patch) | |
| tree | 39d542ba472cd4398a030989e824e661a8751d49 /src/southbridge/intel/fsp_bd82x6x/Kconfig | |
| parent | a4ffe8aa4981130b240eee5ed22c5bbfa1c7598b (diff) | |
Revert "Remove sandybridge and ivybridge FSP code path"
Please don't remove chipsets and mainboards without discussion and input
from the owners. Someone was asking about cougar canyon 2 just a couple
of weeks ago - there's obviously still interest.
This reverts commit fb50124d22014742b6990a95df87a7a828e891b6.
Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/12128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/Kconfig')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/Kconfig | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig new file mode 100644 index 0000000000..85c6ee7862 --- /dev/null +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## Copyright (C) 2013 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config SOUTHBRIDGE_INTEL_FSP_BD82X6X + bool + +if SOUTHBRIDGE_INTEL_FSP_BD82X6X + +config SOUTH_BRIDGE_OPTIONS # dummy + def_bool y + select IOAPIC + select HAVE_HARD_RESET + select HAVE_SMI_HANDLER + select USE_WATCHDOG_ON_BOOT + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select SPI_FLASH + select COMMON_FADT + select HAVE_INTEL_FIRMWARE + +config EHCI_BAR + hex + default 0xfef00000 + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/fsp_bd82x6x/bootblock.c" + +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +config HPET_MIN_TICKS + hex + default 0x80 + +endif |