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authorEd Swierk <eswierk@arastra.com>2008-04-01 02:36:59 +0000
committerEd Swierk <eswierk@arastra.com>2008-04-01 02:36:59 +0000
commitc4e052cd5089019dc67b4fa176bca6d8d19de30d (patch)
tree86802951111145e526401af3029372e6ef51fc05 /src/southbridge/intel/esb6300
parent2c6b33ce3e2eb287e6a0b25d46b96ba7876fe17a (diff)
The early init code of several Intel southbridge chipsets calls
pci_locate_device() to locate the SMBus controller and LPC bridge devices on the PCI bus. Since these devices are always located at a fixed PCI bus:device:function, the code can be simplified by hardcoding the devices. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/esb6300')
-rw-r--r--src/southbridge/intel/esb6300/esb6300_early_smbus.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/src/southbridge/intel/esb6300/esb6300_early_smbus.c b/src/southbridge/intel/esb6300/esb6300_early_smbus.c
index e115e3a2fa..503d573dea 100644
--- a/src/southbridge/intel/esb6300/esb6300_early_smbus.c
+++ b/src/southbridge/intel/esb6300/esb6300_early_smbus.c
@@ -4,12 +4,8 @@
static void enable_smbus(void)
{
- device_t dev;
- dev = pci_locate_device(PCI_ID(0x8086, 0x25a4), 0);
- if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
- }
- uint8_t enable;
+ device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
print_spew("SMBus controller enabled\r\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
pci_write_config8(dev, 0x40, 1);
@@ -19,11 +15,6 @@ static void enable_smbus(void)
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
- dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID) {
- die("ISA bridge not found\r\n");
- }
}
static int smbus_read_byte(unsigned device, unsigned address)