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authorDuncan Laurie <dlaurie@chromium.org>2012-12-19 09:12:31 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 20:16:26 +0100
commit26e7dd703dea8dce30829d8bb73c1f27a2178d72 (patch)
tree924161b457fd106535444b45089d3e0ede1dd8d9 /src/southbridge/intel/esb6300
parenteb58bc5af6b8bf626f38d0c07bf55db2835f53b5 (diff)
haswell: more ULT/LP support and minor tweaks
- Add ME device ID for Lynxpoint LP - Add GPU device IDs for ULT - SATA init tweaks from checking against DXE reference code - Remove the ICH7 from the SPI driver so it works on all lynxpoint without having to add more LPC device ID checks - Add function disable for audio dsp and xhci, remove PCI bridge - Add interrupt route registers for new devices (needs romstage setup) Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2680 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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