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authorStefan Reinauer <stefan.reinauer@coreboot.org>2015-10-28 18:02:35 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-10-30 18:53:19 +0100
commit3e6ba4daccd9fdc451c6c4704e7d02ca6e6e85fc (patch)
tree4bcb04113b46d4d7e927d2ed27c1646d0c9b1841 /src/southbridge/intel/esb6300/chip.h
parent3efcd2eeee8b3c68996cbe763685117eff483c08 (diff)
Drop southbridge intel/esb6300
All mainboards using this southbridge have been removed from the tree already. Change-Id: I4398ef1e270bd0f36c5dd1c6ec3bfec6c2c091e6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12238 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/esb6300/chip.h')
-rw-r--r--src/southbridge/intel/esb6300/chip.h28
1 files changed, 0 insertions, 28 deletions
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h
deleted file mode 100644
index 384a991cec..0000000000
--- a/src/southbridge/intel/esb6300/chip.h
+++ /dev/null
@@ -1,28 +0,0 @@
-struct southbridge_intel_esb6300_config
-{
-#define ESB6300_GPIO_USE_MASK 0x03
-#define ESB6300_GPIO_USE_DEFAULT 0x00
-#define ESB6300_GPIO_USE_AS_NATIVE 0x01
-#define ESB6300_GPIO_USE_AS_GPIO 0x02
-
-#define ESB6300_GPIO_SEL_MASK 0x0c
-#define ESB6300_GPIO_SEL_DEFAULT 0x00
-#define ESB6300_GPIO_SEL_OUTPUT 0x04
-#define ESB6300_GPIO_SEL_INPUT 0x08
-
-#define ESB6300_GPIO_LVL_MASK 0x30
-#define ESB6300_GPIO_LVL_DEFAULT 0x00
-#define ESB6300_GPIO_LVL_LOW 0x10
-#define ESB6300_GPIO_LVL_HIGH 0x20
-#define ESB6300_GPIO_LVL_BLINK 0x30
-
-#define ESB6300_GPIO_INV_MASK 0xc0
-#define ESB6300_GPIO_INV_DEFAULT 0x00
-#define ESB6300_GPIO_INV_OFF 0x40
-#define ESB6300_GPIO_INV_ON 0x80
-
- /* GPIO use select */
- unsigned char gpio[64];
- unsigned int pirq_a_d;
- unsigned int pirq_e_h;
-};