diff options
| author | Yinghai Lu <yinghailu@gmail.com> | 2005-07-08 02:49:49 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2005-07-08 02:49:49 +0000 |
| commit | 13f1c2af8be2cd7f7e99a678f5d428a65b771811 (patch) | |
| tree | 27cad5581f1fa150f573149d48e82f70ba1b1d9f /src/southbridge/intel/esb6300/chip.h | |
| parent | 14cde9e96a777f9d75016a13b23fab0480515f58 (diff) | |
eric patch
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/esb6300/chip.h')
| -rw-r--r-- | src/southbridge/intel/esb6300/chip.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h new file mode 100644 index 0000000000..ff74e615fd --- /dev/null +++ b/src/southbridge/intel/esb6300/chip.h @@ -0,0 +1,30 @@ +struct southbridge_intel_esb6300_config +{ +#define ESB6300_GPIO_USE_MASK 0x03 +#define ESB6300_GPIO_USE_DEFAULT 0x00 +#define ESB6300_GPIO_USE_AS_NATIVE 0x01 +#define ESB6300_GPIO_USE_AS_GPIO 0x02 + +#define ESB6300_GPIO_SEL_MASK 0x0c +#define ESB6300_GPIO_SEL_DEFAULT 0x00 +#define ESB6300_GPIO_SEL_OUTPUT 0x04 +#define ESB6300_GPIO_SEL_INPUT 0x08 + +#define ESB6300_GPIO_LVL_MASK 0x30 +#define ESB6300_GPIO_LVL_DEFAULT 0x00 +#define ESB6300_GPIO_LVL_LOW 0x10 +#define ESB6300_GPIO_LVL_HIGH 0x20 +#define ESB6300_GPIO_LVL_BLINK 0x30 + +#define ESB6300_GPIO_INV_MASK 0xc0 +#define ESB6300_GPIO_INV_DEFAULT 0x00 +#define ESB6300_GPIO_INV_OFF 0x40 +#define ESB6300_GPIO_INV_ON 0x80 + + /* GPIO use select */ + unsigned char gpio[64]; + unsigned int pirq_a_d; + unsigned int pirq_e_h; +}; +extern struct chip_operations southbridge_intel_esb6300_ops; + |