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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-01 16:56:36 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-07 16:01:35 +0000
commit551a75923ec7e7bacaf6da79b38eda5c3b3821ad (patch)
tree32d10123e44a9e7e8c699e532b2c8fe8f2ac781c /src/southbridge/intel/common
parent30bc9f415d9564de90fc0c6c6a92462ce3ce7c06 (diff)
sb/{ICH7,NM10,PCH}: Use common watchdog_off function
Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian
Diffstat (limited to 'src/southbridge/intel/common')
-rw-r--r--src/southbridge/intel/common/Kconfig4
-rw-r--r--src/southbridge/intel/common/Makefile.inc2
-rw-r--r--src/southbridge/intel/common/tco.h27
-rw-r--r--src/southbridge/intel/common/watchdog.c59
4 files changed, 92 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 0bda06e10a..c3bd90dca8 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -65,6 +65,10 @@ config INTEL_CHIPSET_LOCKDOWN
and S3 resume (always done by coreboot). Select this to let coreboot
to do this on normal boot path.
+config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
+ bool
+ depends on SOUTHBRIDGE_INTEL_COMMON
+
if SOUTHBRIDGE_INTEL_COMMON_FINALIZE
choice
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 1085f6c66a..4cf6e6f57e 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -27,6 +27,8 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c
+ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c
+
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
verstage-y += pmbase.c
diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h
new file mode 100644
index 0000000000..9d6f15326e
--- /dev/null
+++ b/src/southbridge/intel/common/tco.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2019 Elyes Haouas <ehaouas@noos.fr>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H
+#define SOUTHBRIDGE_INTEL_COMMON_TCO_H
+
+#define PMBASE_TCO_OFFSET 0x60
+#define TCO1_STS 0x04
+#define TCO1_TIMEOUT (1 << 3)
+#define TCO2_STS 0x06
+#define SECOND_TO_STS (1 << 1)
+#define TCO1_CNT 0x08
+#define TCO_TMR_HLT (1 << 11)
+
+#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */
diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c
new file mode 100644
index 0000000000..778a7a9f7f
--- /dev/null
+++ b/src/southbridge/intel/common/watchdog.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <southbridge/intel/common/pmbase.h>
+#include <southbridge/intel/common/tco.h>
+#include <watchdog.h>
+
+/*
+ * Disable ICH-NM10-PCH watchdog timer
+ */
+void watchdog_off(void)
+{
+ unsigned int value;
+ struct device *dev;
+
+ /* Get LPC device. */
+ dev = pcidev_on_root(0x1f, 0);
+
+ value = pci_read_config16(dev, PCI_COMMAND);
+
+ if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) {
+ /* Enable I/O space. */
+ value |= PCI_COMMAND_IO;
+ } else {
+ /* Disable interrupt. */
+ value |= PCI_COMMAND_INT_DISABLE;
+ }
+ pci_write_config16(dev, PCI_COMMAND, value);
+
+ /* Disable the watchdog timer. */
+ value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
+ value |= TCO_TMR_HLT;
+ write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
+
+ /* Clear TCO timeout status. */
+ write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
+ write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
+
+ printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");
+}