diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 12:56:19 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-11-27 12:09:53 +0000 |
| commit | 31312b21d147938cb4d88ed90e570ac7804c930d (patch) | |
| tree | 57a714d7939d23838e990686b089f9364dc049ef /src/southbridge/intel/common | |
| parent | 516f06e0fb7e4ba4e9ae6c024ab36a079b7cbb76 (diff) | |
sb/intel/i82801gx: Use common Intel SMM code
Use the common Intel code to set up smm and the smihandler. This is
expected to break S3 resume and other smihandler related
functionality as this code is meant to be used with
CONFIG_SMM_TSEG. Platforms (i945, pineview, x4x) using this
southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent
patches.
Tested on Intel D945GCLF, still boots fine but breaks S3 resume
support because it hangs on SMI.
Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/pmutil.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c578982e92..2e761ccef2 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -63,8 +63,14 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#define PM2_CNT 0x20 // mobile only +#define GPE0_STS 0x28 +#else #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 +#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */ +#define USB4_STS (1 << 14) /* i82801gx only */ #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) #define BATLOW_STS (1 << 10) @@ -74,7 +80,11 @@ #define TCOSCI_STS (1 << 6) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#define GPE0_EN 0x2c +#else #define GPE0_EN 0x28 +#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */ #define PME_B0_EN (1 << 13) #define PME_EN (1 << 11) #define TCOSCI_EN (1 << 6) |