diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2018-10-01 19:17:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:25 +0000 |
| commit | 45022ae056cdbf58429b77daf2da176306312801 (patch) | |
| tree | 4218666e3c14e41232778c4ceff301292b3c61d9 /src/southbridge/intel/common | |
| parent | 33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff) | |
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/common/reset.c | 20 |
3 files changed, 31 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 0f75537247..47a714b323 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -1,5 +1,10 @@ config SOUTHBRIDGE_INTEL_COMMON def_bool n + select SOUTHBRIDGE_INTEL_COMMON_RESET + +config SOUTHBRIDGE_INTEL_COMMON_RESET + bool + select HAVE_CF9_RESET config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 961b71bbd8..249d2496ef 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -16,6 +16,12 @@ # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware +verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-y += pmbase.c diff --git a/src/southbridge/intel/common/reset.c b/src/southbridge/intel/common/reset.c new file mode 100644 index 0000000000..5a23afa38e --- /dev/null +++ b/src/southbridge/intel/common/reset.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cf9_reset.h> +#include <reset.h> + +void do_board_reset(void) +{ + system_reset(); +} |