diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-12 23:48:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-21 15:51:12 +0000 |
| commit | 1f2ae9107400390240d6338fbf0406aafd2ac01e (patch) | |
| tree | 1c59dd3d93abbc74472f7917c1b6f064bdcdf396 /src/southbridge/intel/common | |
| parent | 58a89537931cd243c6ddbb9ff435bc5862fc64b0 (diff) | |
sb/intel/common: Make RCBA manipulation MACROs common
No Change in BUILD_TIMELESS.
Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/rcba.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h new file mode 100644 index 0000000000..b6cba8ea5f --- /dev/null +++ b/src/southbridge/intel/common/rcba.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H +#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H + +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else +#define DEFAULT_RCBA 0xfed1c000 +#endif + +#ifndef __ACPI__ + +#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) +#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) +#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x))) + +#define RCBA_AND_OR(bits, x, and, or) \ + (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) +#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) +#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) +#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) +#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) + + +#endif /* __ACPI__ */ +#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ |