diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-12 22:25:28 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-15 11:20:04 +0000 |
| commit | eef4343a9f0e94a5a2137793d15c582278715d28 (patch) | |
| tree | d39a79a7cea1001c5851775c94bc4cb902ae71db /src/southbridge/intel/common | |
| parent | 70dca08f2559ac7d704a2fadc8af8adc992dc619 (diff) | |
nb/intel/pineview: Extract HPET setup and delay function
To allow other platforms to reuse this code, extract it into a separate
compilation unit. Since HPET is enabled through the southbridge, place
the code in the southbridge scope. Finally, select the newly-added
Kconfig option from i82801gx and replace lpc.c `enable_hpet` function.
Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/hpet.c | 43 | ||||
| -rw-r--r-- | src/southbridge/intel/common/hpet.h | 11 |
4 files changed, 59 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 3030d25757..a14513dead 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n +config SOUTHBRIDGE_INTEL_COMMON_HPET + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 6c57481e55..f11ffa6aef 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -5,6 +5,8 @@ subdirs-y += firmware all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/hpet.c b/src/southbridge/intel/common/hpet.c new file mode 100644 index 0000000000..c48edae59d --- /dev/null +++ b/src/southbridge/intel/common/hpet.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/rcba.h> +#include <stdint.h> + +#include "hpet.h" + +#define HPTC 0x3404 + +#define HPET_BASE 0xfed00000 +#define HPET32(x) (*((volatile u32 *)(HPET_BASE + (x)))) + +void enable_hpet(void) +{ + u32 reg32; + reg32 = RCBA32(HPTC); + reg32 &= ~0x03; + reg32 |= (1 << 7); + RCBA32(HPTC) = reg32; + /* Read back for posted write to take effect */ + RCBA32(HPTC); + HPET32(0x10) = HPET32(0x10) | 1; +} + +void hpet_udelay(u32 delay) +{ + u32 start, finish, now; + + delay *= 15; /* now in usec */ + + start = HPET32(0xf0); + finish = start + delay; + while (1) { + now = HPET32(0xf0); + if (finish > start) { + if (now >= finish) + break; + } else { + if ((now < start) && (now >= finish)) + break; + } + } +} diff --git a/src/southbridge/intel/common/hpet.h b/src/southbridge/intel/common/hpet.h new file mode 100644 index 0000000000..1a69178e2e --- /dev/null +++ b/src/southbridge/intel/common/hpet.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_HPET_H +#define SOUTHBRIDGE_INTEL_COMMON_HPET_H + +#include <stdint.h> + +void enable_hpet(void); +void hpet_udelay(u32 delay); + +#endif /* SOUTHBRIDGE_INTEL_COMMON_HPET_H */ |