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authorArthur Heymans <arthur@aheymans.xyz>2018-01-25 00:33:45 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-07-30 19:11:00 +0000
commitaade90e68d26a90fbea0dccdaae3493bdf31829a (patch)
tree5e31d203c4beecb94250a458e67cc7d639f0b250 /src/southbridge/intel/common
parent6cd2c2f6ff792d1a170cd090e3347cfe2e14ac15 (diff)
nb/intel/gm45: Use common code for SMM in TSEG
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common')
-rw-r--r--src/southbridge/intel/common/smihandler.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index fb2fe59bd1..0fd8ab0506 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -484,7 +484,11 @@ static smi_handler_t southbridge_smi[32] = {
* @param node
* @param state_save
*/
+#if IS_ENABLED(CONFIG_SMM_TSEG)
void southbridge_smi_handler(void)
+#else
+void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+#endif
{
int i, dump = 0;
u32 smi_sts;