summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/common
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-06 19:00:31 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-09 21:29:53 +0000
commit7cdcc38f292d7a8ffd285d17c848e60e41eec759 (patch)
tree13bba3b16f89d74367fdc043e10d707534a24525 /src/southbridge/intel/common
parentc528426b264c897b6c17ef14846afea3711042cb (diff)
sb/intel/common: Add smbus_host_reset()
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common')
-rw-r--r--src/southbridge/intel/common/smbus.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c
index f294f3163b..f6805ad50f 100644
--- a/src/southbridge/intel/common/smbus.c
+++ b/src/southbridge/intel/common/smbus.c
@@ -92,6 +92,15 @@ static void host_and_or(uintptr_t base, u8 reg, u8 mask, u8 or)
host_outb(base, reg, value);
}
+void smbus_host_reset(uintptr_t base)
+{
+ /* Disable interrupt generation. */
+ host_outb(base, SMBHSTCTL, 0);
+
+ /* Clear any lingering errors, so transactions can run. */
+ host_and_or(base, SMBHSTSTAT, 0xff, 0);
+}
+
static int host_completed(u8 status)
{
if (status & SMBHSTSTS_HOST_BUSY)