sb,soc/intel: Address TCO SECOND_TO_STS name collision

Later soc/intel/common/smbus addresses TCO2_STS as a separate
16-bit register, while baytrail and braswell assumes 32-bit
wide TCO1_STS to extend as TCO2_STS.

In src/soc/intel/denverton_ns:
  #define TCO2_STS_SECOND_TO 0x02

In soc/intel/baytrail,braswell:
  #define SECOND_TO_STS (1 << 17)

Elsewehere
  #define SECOND_TO_STS (1 << 1)

It's expected that we remove the first (1 << 17) case and only
access TCO2_STS as a separate 16-bit register. For now, use
unique names to avoid confusion.

Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c
index b40c5fe3b3..a9886916ca 100644
--- a/src/southbridge/intel/common/watchdog.c
+++ b/src/southbridge/intel/common/watchdog.c
@@ -33,7 +33,7 @@ void watchdog_off(void)
 
 	/* Clear TCO timeout status. */
 	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
-	write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
+	write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
 
 	printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");
 }