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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-19 18:39:22 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-28 10:08:23 +0000 |
| commit | e8a3af10691a4831a85d8760f7fcb20f78065f78 (patch) | |
| tree | dff1c9bbfdee73e0283223c334b168ab4b0c4662 /src/southbridge/intel/common/tco.h | |
| parent | 560c3f5ccfff0fc289bb46f1b1b6c4236817590a (diff) | |
sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT
Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.
For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().
Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common/tco.h')
| -rw-r--r-- | src/southbridge/intel/common/tco.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 03d312271e..4c3f6391b4 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -3,7 +3,15 @@ #ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H #define SOUTHBRIDGE_INTEL_COMMON_TCO_H +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) +/* Could get conflicting values. */ +#undef TCO1_STS +#undef TCO2_STS +#undef TCO1_CNT +#endif + #define PMBASE_TCO_OFFSET 0x60 + #define TCO1_STS 0x04 #define TCO1_TIMEOUT (1 << 3) #define TCO2_STS 0x06 |