diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-12 17:01:31 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-06 23:26:15 +0000 |
| commit | 16fe79048f5254661ff2342aa481cbb44657b7ff (patch) | |
| tree | 5ad72bc5c5a97ca9a7a47f5ab24bbe622f12e9e9 /src/southbridge/intel/common/smbus.h | |
| parent | 12d010306b3892b01350e96d83275206215d9f31 (diff) | |
sb/intel/*: Use common SMBus functions
All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common/smbus.h')
| -rw-r--r-- | src/southbridge/intel/common/smbus.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h new file mode 100644 index 0000000000..f2e903c82b --- /dev/null +++ b/src/southbridge/intel/common/smbus.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef INTEL_COMMON_SMBUS_H +#define INTEL_COMMON_SMBUS_H + +/* SMBus register offsets. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf +#define SMBSLVCMD 0x11 + +int do_smbus_read_byte(unsigned int smbus_base, u8 device, + unsigned int address); +int do_smbus_write_byte(unsigned int smbus_base, u8 device, + unsigned int address, unsigned int data); +int do_smbus_block_read(unsigned int smbus_base, u8 device, + u8 cmd, unsigned int bytes, u8 *buf); +int do_smbus_block_write(unsigned int smbus_base, u8 device, + u8 cmd, unsigned int bytes, const u8 *buf); +/* Only since ICH5 */ +int do_i2c_block_read(unsigned int smbus_base, u8 device, + unsigned int offset, u32 bytes, u8 *buf); +#endif |