sb/intel/common/pirq_gen: Rework generating pin-route tables

This creates a pin-route matrix first and then generates the ACPI
entries based on that. This approach has the advantage of being
simpler (no need for checks on double entries) and requiring less
access to the pci config space.

A few thing that are also fixed:
* Don't declare DEFAULT_RCBA redundantly.
* Only loop over PCI devices on bus 0
* Add a license header to rcba_pirq.c
* Remove inappropriate use of typedefs
* Fix the pin field: needs to be a byte
* Fix the source field: it should either be a byte or a path
(according to Advanced Configuration and Power Interface Specification
rev 2.0c)

Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22979
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 26 insertions, 12 deletions

diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c
index 44d2f3d911..d27c4511ba 100644
--- a/src/southbridge/intel/common/rcba_pirq.c
+++ b/src/southbridge/intel/common/rcba_pirq.c
@@ -1,3 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -12,31 +27,30 @@ static const u32 pirq_dir_route_reg[MAX_SLOT - MIN_SLOT + 1] = {
 	D26IR, D27IR, D28IR, D29IR, D30IR, D31IR,
 };
 
-enum pirq intel_common_map_pirq(const device_t dev, const pci_pin_t pci_pin)
+enum pirq intel_common_map_pirq(const struct device *dev,
+				const enum pci_pin pci_pin)
 {
 	u8 slot = PCI_SLOT(dev->path.pci.devfn);
 	u8 shift = 4 * (pci_pin - PCI_INT_A);
 	u8 pirq;
 	u16 reg;
 
-	if (pci_pin < 1 || pci_pin > 4) {
-		printk(BIOS_ERR, "Slot %d PCI pin %d out of bounds\n",
+	if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) {
+		printk(BIOS_ERR,
+			"ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n",
 			slot, pci_pin);
 		return PIRQ_NONE;
 	}
 
-	if (slot < MIN_SLOT || slot > MAX_SLOT) {
+	/* Slot 24 should not exist and has no D24IR but better be safe here */
+	if (slot < MIN_SLOT || slot > MAX_SLOT || slot == 24) {
 		/* non-PCH devices use 1:1 mapping. */
-		return pci_pin;
+		return (enum pirq)pci_pin;
 	}
 
 	reg = pirq_dir_route_reg[slot - MIN_SLOT];
 
-	pirq = ((RCBA16(reg) >> shift) & 0xf);
-	if (pirq > 8) {
-		printk(BIOS_ERR, "Reg 0x%04x PIRQ %c out of bounds\n",
-			reg, 'A' + pirq);
-		return PIRQ_NONE;
-	}
-	return PIRQ_A + pirq;
+	pirq = (RCBA16(reg) >> shift) & 0x7;
+
+	return (enum pirq)(PIRQ_A + pirq);
 }