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| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2024-06-21 19:42:54 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-07-31 14:28:24 +0000 |
| commit | 365e511ee4cd7e63c57b58f90f05e1f6ce52c8c6 (patch) | |
| tree | 995183e47709d5b112a01c97bfa3ebf145dd99b4 /src/southbridge/intel/common/pciehp.h | |
| parent | dc2ee2096ac629ba01c6734b1a9b318d79e7382e (diff) | |
util/superiotool/fintek: Add f81866 register table
In accordance with the F81866A datasheet:
Release Date: Jan, 2012, Version: V0.14P [1].
[1] https://web.archive.org/web/20240707051837/http://www.
jetwaycomputer.com/download/Fintek/F81866_wdt_gpio.zip
Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83004
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/pciehp.h')
0 files changed, 0 insertions, 0 deletions