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| author | Nancy.Lin <nancy.lin@mediatek.com> | 2021-05-07 10:46:29 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-13 01:44:15 +0000 |
| commit | a1e7ab6f82786032fe7d02ec70abc65b5ca3a9ad (patch) | |
| tree | ab4b42e339afff99ae15e40dffe3dca36cc4f1ee /src/southbridge/intel/common/pciehp.h | |
| parent | 00b43c98437484c59da0d1332936ee9a15d453fe (diff) | |
soc/mediatek/mt8195: change vpp_sel default mux for 4k support
vpp_sel and ethdr_sel are vdosys clock source select mux.
Steps to change to support 4K source.
1. Change vpp_sel source to mainpll_d4 to run at 546MHz
2. Change ethdr_sel source to univpll_d6 to run at 416MHz
Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
Change-Id: Ib6518ed6204528489c41e7161534bbd3734ac851
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54082
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/pciehp.h')
0 files changed, 0 insertions, 0 deletions