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| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2021-05-10 20:06:35 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-13 01:43:57 +0000 |
| commit | 00b43c98437484c59da0d1332936ee9a15d453fe (patch) | |
| tree | bd69701cac3ee266def3ff30b92575d37b22f971 /src/southbridge/intel/common/pciehp.h | |
| parent | 8c3b747ccffc6a0fda8bde74caaf685dde78930f (diff) | |
soc/mediatek/mt8195: configure DMA buffer in DRAM
Set DRAM DMA to be non-cacheable to load blob correctly.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54052
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/pciehp.h')
0 files changed, 0 insertions, 0 deletions