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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2019-12-16 16:39:53 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 17:57:17 +0000 |
| commit | e9b1e0fe8873cb3131b0dc4741e83540e0d90a31 (patch) | |
| tree | 23cb5fff46fc92a33ca9e2c78223c03b5d27a16c /src/southbridge/intel/common/pciehp.c | |
| parent | 6ee5559d6a3c1ba452a53db58ec6b41d629d92b2 (diff) | |
soc/intel/tigerlake: Update FSP stack and heap size
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB
and heap size to be minimum 128 KiB.
Updating both Kconfig to meet size requirements.
Also updated required CAR region size during boot block due to increment
in stack & heap requirement by fsp
Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/pciehp.c')
0 files changed, 0 insertions, 0 deletions