diff options
| author | Hung-Te Lin <hungte@chromium.org> | 2019-07-09 16:38:36 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-11 15:09:05 +0000 |
| commit | 447badd1cfbf70a26f3e6fb0b84d8166dc732bc4 (patch) | |
| tree | cd5ef98bfad902d8ccf0b75ee06e8a5ccd46f0df /src/southbridge/intel/common/pciehp.c | |
| parent | ff423f749a5c74f6a4dda59b996fcbed72c94e94 (diff) | |
board/kukui: Remove ADC tolerance from boardid
The tolerance of ADC is +-10mV, but the resistors may also
introduce 1% variation, and causing the final measured
voltage to vary around 5%.
By the advisory from hardware team, checking the tolerance
seems not really solving or helping anything so we should
just ignore that and try to find best matched ID (this
also aligns to what Gru did).
BUG=b:136990271
TEST=Booted on Krane and no longer seeing ADC out of range
BRANCH=None
Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/pciehp.c')
0 files changed, 0 insertions, 0 deletions