aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/common/me.c
diff options
context:
space:
mode:
authorEvgeny Zinoviev <me@ch1p.io>2021-02-07 01:49:30 +0300
committerEvgeny Zinoviev <me@ch1p.io>2021-02-07 01:49:30 +0300
commitee835aed102f4651f30234eda1110fa106575fdd (patch)
treee3368029dfe7b14b77892b6f48dbd0d11614057a /src/southbridge/intel/common/me.c
parent8f96216188ae440be6af63af650e26f05a86fd81 (diff)
parentb01b13866a6049ac81bd11861a29c3f4e591f951 (diff)
Merge branch 'me-disable' into mbp101_medisable_1
Diffstat (limited to 'src/southbridge/intel/common/me.c')
-rw-r--r--src/southbridge/intel/common/me.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/me.c b/src/southbridge/intel/common/me.c
new file mode 100644
index 0000000000..d49508748a
--- /dev/null
+++ b/src/southbridge/intel/common/me.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define __SIMPLE_DEVICE__
+
+#include <device/pci_ops.h>
+#include <types.h>
+
+#include "me.h"
+
+#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
+
+#define ETR3 0xac
+#define ETR3_CWORWRE (1 << 18)
+#define ETR3_CF9GR (1 << 20)
+#define ETR3_CF9LOCK (1 << 31)
+
+void set_global_reset(const bool enable)
+{
+ u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+
+ /* Clear CF9 Without Resume Well Reset Enable */
+ etr3 &= ~ETR3_CWORWRE;
+
+ /* CF9GR indicates a Global Reset */
+ if (enable)
+ etr3 |= ETR3_CF9GR;
+ else
+ etr3 &= ~ETR3_CF9GR;
+
+ pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+}