diff options
author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-05-06 20:48:32 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-12 20:08:47 +0000 |
commit | 79412ed3649ab423fb2eee73f971a928108fd041 (patch) | |
tree | 113e77345202f3cb80713c005986b114ae328f7e /src/southbridge/intel/common/firmware | |
parent | 04953ebf5f343dcb37e1288705a160b4cf1b64cf (diff) |
soc/intel/tigerlake: Correct IRQ interrupt
Current Interrupt setting use 2nd parameters as device function number.
- Correct as interrupt pin number according to _PRT package format.
{Address, pin, Source, Source index}
- Use irq number directly rather than irq definition as its number
is not for PCI device.
The issue found while enabling GBE and GBE interrupt is not working
without this change.
Reference
- ACPI spec 6.2.13 _PRT
- FSP reference code:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
- BIOS reference code:
https://github.com/otcshare/CCG-TGL-Generic-Full/blob/master/
TigerLakeBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
TEST=boot to OS with GBE enabled and check GBE interrupt
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8084b30c668c155ebabbee90b5f70054813b328e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/firmware')
0 files changed, 0 insertions, 0 deletions