src/southbridge: Use SPDX for GPL-2.0-only files

Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

5 files changed, 10 insertions, 70 deletions

diff --git a/src/southbridge/intel/common/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl
index ad33d4b4f9..a3076f988e 100644
--- a/src/southbridge/intel/common/acpi/pcie.asl
+++ b/src/southbridge/intel/common/acpi/pcie.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
 
 /* Intel 6/7 Series PCH PCIe support */
 
diff --git a/src/southbridge/intel/common/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl
index 86cc0bdf87..34ab79b78c 100644
--- a/src/southbridge/intel/common/acpi/pcie_port.asl
+++ b/src/southbridge/intel/common/acpi/pcie_port.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
 
 /* Included in each PCIe Root Port device */
 
diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl
index 011f708c59..7451e44260 100644
--- a/src/southbridge/intel/common/acpi/platform.asl
+++ b/src/southbridge/intel/common/acpi/platform.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
 
 /* The APM port can be used for generating software SMIs */
 
diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl
index 89dfc57169..ed8b1b8945 100644
--- a/src/southbridge/intel/common/acpi/sleepstates.asl
+++ b/src/southbridge/intel/common/acpi/sleepstates.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
 
 Name(\_S0, Package(){0x0,0x0,0x0,0x0})
 #if !CONFIG(HAVE_ACPI_RESUME)
diff --git a/src/southbridge/intel/common/acpi/smbus.asl b/src/southbridge/intel/common/acpi/smbus.asl
index 8a1d1f9b64..9fc516fe54 100644
--- a/src/southbridge/intel/common/acpi/smbus.asl
+++ b/src/southbridge/intel/common/acpi/smbus.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
 
 // Intel SMBus Controller 0:1f.3