diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-05 20:43:00 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-11 15:12:47 +0000 |
| commit | 79b2a150c7a18a61604b0d81f52a7c6ad8522b60 (patch) | |
| tree | 35fdf0dcfa4e0eaf2605c4f0c62cf2690ebcd409 /src/southbridge/intel/common/Makefile.inc | |
| parent | 30ff00650a7129475bf01ce9d258ac27b59c786b (diff) | |
sb/intel/x/smbus.c: Factor out common code
Since common smbus.c gets built for romstage as well, create a new file
to hold this common code. Account for ICH7 not having a memory BAR, too.
Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1ededd23ec..6c57481e55 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -9,6 +9,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus_ops.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c |