nb/intel/haswell: Add an option for where verstage starts

Previously Haswell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.

This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.

Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.

Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index ac339a2915..1085f6c66a 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -29,6 +29,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
 
+verstage-y += pmbase.c
 romstage-y += pmbase.c
 ramstage-y += pmbase.c
 postcar-y += pmbase.c
@@ -59,6 +60,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c
 
 smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c
 
+verstage-y += rtc.c
 romstage-y += rtc.c
 ramstage-y += rtc.c
 postcar-y += rtc.c