diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-16 16:13:35 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-18 10:11:39 +0000 |
| commit | c027ece821ed3f65f7c08fb0b6d9b707401dddc4 (patch) | |
| tree | 0e3918a86530a3deebdd3a75cb20ac2ff57bc541 /src/southbridge/intel/common/Kconfig | |
| parent | 442bde7b62a5eb04a48abb147a379772eda568d9 (diff) | |
southbridge: Ensure common Kconfig gets included last
Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/common/Kconfig')
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 121 |
1 files changed, 0 insertions, 121 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig deleted file mode 100644 index 5d7a4ee784..0000000000 --- a/src/southbridge/intel/common/Kconfig +++ /dev/null @@ -1,121 +0,0 @@ -config SOUTHBRIDGE_INTEL_COMMON_RESET - def_bool n - select HAVE_CF9_RESET - -config SOUTHBRIDGE_INTEL_COMMON_RTC - def_bool n - -config SOUTHBRIDGE_INTEL_COMMON_PMCLIB - def_bool n - depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE - -config SOUTHBRIDGE_INTEL_COMMON_PMBASE - def_bool n - -config SOUTHBRIDGE_INTEL_COMMON_GPIO - def_bool n - -config SOUTHBRIDGE_INTEL_COMMON_ME - def_bool n - -config SOUTHBRIDGE_INTEL_COMMON_HPET - def_bool n - -config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - def_bool n - -config SOUTHBRIDGE_INTEL_COMMON_SMBUS - def_bool n - select HAVE_DEBUG_SMBUS - -config SOUTHBRIDGE_INTEL_COMMON_SPI - def_bool n - select SPI_FLASH - select BOOT_DEVICE_SUPPORTS_WRITES - -config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 - def_bool n - select SOUTHBRIDGE_INTEL_COMMON_SPI - -config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - def_bool n - select SOUTHBRIDGE_INTEL_COMMON_SPI - -config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT - def_bool n - select SOUTHBRIDGE_INTEL_COMMON_SPI - -config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN - def_bool n - -config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ - def_bool n - select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN - -config HAVE_INTEL_CHIPSET_LOCKDOWN - def_bool n - -config SOUTHBRIDGE_INTEL_COMMON_SMM - def_bool n - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select SOUTHBRIDGE_INTEL_COMMON_PMBASE - -config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT - bool - -config SOUTHBRIDGE_INTEL_COMMON_FINALIZE - bool - -config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG - def_bool n - select HAVE_USBDEBUG - -config INTEL_DESCRIPTOR_MODE_CAPABLE - def_bool n - help - This config simply states that the platform is *capable* of running in - descriptor mode (when the descriptor in flash is valid). - -config INTEL_DESCRIPTOR_MODE_REQUIRED - def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE - help - This config states descriptor mode is *required* for the platform to - function properly, or to function at all. - -config VALIDATE_INTEL_DESCRIPTOR - depends on INTEL_DESCRIPTOR_MODE_CAPABLE - bool "Validate Intel firmware descriptor" - default n - help - This config enables validating the Intel firmware descriptor against the - fmap layout. If the firmware descriptor layout does not match the fmap - then the bootimage cannot be built. - -config INTEL_CHIPSET_LOCKDOWN - depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS - #ChromeOS's payload seems to handle finalization on its on. - bool "Lock down chipset in coreboot" - default y - help - Some registers within host bridge on particular chipsets should be - locked down on each normal boot path (done by either coreboot or payload) - and S3 resume (always done by coreboot). Select this to let coreboot - to do this on normal boot path. - -config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG - bool - depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE - -config FIXED_RCBA_MMIO_BASE - hex - default 0xfed1c000 - -config RCBA_LENGTH - hex - default 0x4000 - -config FIXED_SMBUS_IO_BASE - hex - depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS - default 0x400 |