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authorElyes HAOUAS <ehaouas@noos.fr>2019-03-21 11:10:03 +0100
committerNico Huber <nico.h@gmx.de>2019-04-06 16:09:12 +0000
commitbf0970e762a6611cef06af761bc2dec068d439bb (patch)
tree44d4854b7027794bc5a76b44a4e8fd07935cd60c /src/southbridge/intel/bd82x6x
parent161eafb0fb9563decbb953d5dccac4762b770e0c (diff)
src: Use include <delay.h> when appropriate
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 23942feffb..88436213a0 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -18,12 +18,11 @@
#include <arch/cbfs.h>
#include <ip_checksum.h>
#include <device/pci_def.h>
-#include <delay.h>
-
-#include "pch.h"
/* For DMI bar. */
#include <northbridge/intel/sandybridge/sandybridge.h>
+#include "pch.h"
+
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
static void