diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-12 00:25:13 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-13 18:30:57 +0000 |
| commit | b52784136ee017d17078f9aec6533fd3b1b896c4 (patch) | |
| tree | 82aec6153313ec369f37d055dc8eb376a427bed8 /src/southbridge/intel/bd82x6x | |
| parent | 84935f7de5d4906d77e4abe76a475eac8592ec6a (diff) | |
sb/intel: Add CBMC entries in GNVS
While unused, this allows use of a common initialisation
code for GNVS allocation.
Change-Id: Ie84b5a3e16d3baa12bcd5dadac0b1f7edb323272
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/nvs.h | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index ec193c4228..9194f3f5ce 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -110,6 +110,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value + CBMC, 32, /* ChromeOS specific */ Offset (0x100), diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index b75e0ab025..949467b61c 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -100,8 +100,10 @@ struct __packed global_nvs { /* XHCI */ u8 xhci; u8 rsvd12[65]; + u8 tpiq; /* 0xf5 - trackpad IRQ value */ - u8 rsvd13[10]; /* 0xf6 - rsvd */ + u32 cbmc; + u8 rsvd13[6]; /* 0xfa - rsvd */ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; |