diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-10 12:43:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-12 07:56:33 +0000 |
| commit | 9382f0c251f64ac3f469a19ab08da9d7a548a99c (patch) | |
| tree | c6e5551036bf09beee5b31547ff1b658e4b59e93 /src/southbridge/intel/bd82x6x | |
| parent | 04f1de3e149140f58358659c5977515ea36f17f7 (diff) | |
sb/intel/lynxpoint: Do not mask out TCO status bits
Not all TCO status bits have a corresponding enable bit. Masking out the
status register with the enable register causes these events to be lost.
Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected.
Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
0 files changed, 0 insertions, 0 deletions