diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-06-23 15:22:43 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:49:28 +0200 |
| commit | 51cb26d92a2ddac8d71fe0e5970ed208110add71 (patch) | |
| tree | d64e41f2ff26f489a17f8f11d4ca3a23680b0658 /src/southbridge/intel/bd82x6x | |
| parent | 181bbdd51cb4ec318e8b44c1ca652310bf6abb22 (diff) | |
SMM: Fix state save map for sandybridge and TSEG
There are enough differences that it is worth defining the
proper map for the sandybridge/ivybridge CPUs. The state
save map was not being addressed properly for TSEG and
needs to use the right offset instead of pointing in ASEG.
To do this properly add a required southbridge export to
return the TSEG base and use that where appropriate.
Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1309
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smihandler.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 6cf74a508a..b4dc2ac1c9 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -32,6 +32,13 @@ #include "nvs.h" +/* We are using PCIe accesses for now + * 1. the chipset can do it + * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind + */ +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/pcie_config.c> + /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -47,6 +54,12 @@ void *smi1 = (void *)0x0; #if CONFIG_SMM_TSEG static u32 tseg_base = 0; +u32 smi_get_tseg_base(void) +{ + if (!tseg_base) + tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; + return tseg_base; +} static inline void tseg_fixup(void **ptr) { /* Adjust pointer with TSEG base */ @@ -208,13 +221,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -672,11 +678,6 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav /* Update global variable pmbase */ pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; -#if CONFIG_SMM_TSEG - /* Update global variable TSEG base */ - tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; -#endif - /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ @@ -688,7 +689,8 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav if (southbridge_smi[i]) { #if CONFIG_SMM_TSEG smi_handler_t handler = (smi_handler_t) - ((u8*)southbridge_smi[i] + tseg_base); + ((u8*)southbridge_smi[i] + + smi_get_tseg_base()); if (handler) handler(node, state_save); #else |