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authorPatrick Rudolph <siro@das-labor.org>2017-01-02 18:41:37 +0100
committerNico Huber <nico.h@gmx.de>2017-01-03 15:10:15 +0100
commitdf369af79e98960afde403d4375ed03f1a648e2a (patch)
treeb1c22ad367a9e20745fcc66f30192618f33c3d5d /src/southbridge/intel/bd82x6x
parent2ed7295cd995f1e28fe442ce50a4a7aa3362395c (diff)
sb/intel/common/gpio: Support ICH9M and prior
Write gpio level twice to make sure the level is set after pins have been configred as GPIO and to minimize glitches on newer hardware. Required to set correct GPIO layout on T500. Tested on T500. Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18012 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
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