summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-05 08:05:45 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-09 14:37:33 +0000
commitcbf957158806bcd5c733c45baa324559904c609c (patch)
tree89649e264f785ceb76ce223094b3640135a1b920 /src/southbridge/intel/bd82x6x
parent2a0e3b25ea282491cba9d32a8f35d9a238db83c7 (diff)
drivers/pc80/rtc: Separate {get|set}_option() prototypes
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/bd82x6x/sata.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index ef66ca512a..01576a683a 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -20,7 +20,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
-#include <pc80/mc146818rtc.h>
+#include <option.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 3ec065f287..f5243f6507 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -20,7 +20,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <pc80/mc146818rtc.h>
+#include <option.h>
#include <acpi/sata.h>
#include <types.h>