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authorStefan Reinauer <reinauer@chromium.org>2012-09-19 10:49:12 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-09 19:04:15 +0100
commit9d81c19a88dc550353922de2122d4d6e82173151 (patch)
tree2da8189bf151184d99f3244b3ff78648012bc261 /src/southbridge/intel/bd82x6x
parent0acdcf614c9966112add57226e7473bccd86dd64 (diff)
PCH: Add register descriptions used by IGD OpRegion
These bits are used by the IGD OpRegion code Change-Id: I89a11fc5021d51e0c1675ba56f6a3bc3b79bb8aa Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1751 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index c9044ed1d3..84815545c3 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -472,6 +472,7 @@ int smbus_read_byte(unsigned device, unsigned address);
#define GPE0_EN 0x28
#define PME_B0_EN (1 << 13)
#define PME_EN (1 << 11)
+#define TCOSCI_EN (1 << 6)
#define SMI_EN 0x30
#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
@@ -494,6 +495,7 @@ int smbus_read_byte(unsigned device, unsigned address);
#define SS_CNT 0x50
#define C3_RES 0x54
#define TCO1_STS 0x64
+#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
/*