arch/x86: Replace some __SMM__ guards

We generally do not guard source in attempts to reduce
the final object sizes, but rely on garbage collection.

Most of the __unused attributes inserted here will be
removed when remaining __SIMPLE_DEVICE__ guards can
be removed.

Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 23 insertions, 36 deletions

diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 8adb95bdb3..15f99cdf78 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -26,6 +26,8 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include <string.h>
@@ -33,11 +35,6 @@
 #include <elog.h>
 #include <halt.h>
 
-#ifndef __SMM__
-#include <device/device.h>
-#include <device/pci.h>
-#endif
-
 #include "me.h"
 #include "pch.h"
 
@@ -45,9 +42,8 @@
 #include <vendorcode/google/chromeos/gnvs.h>
 #endif
 
-#ifndef __SMM__
 /* Path that the BIOS should take based on ME state */
-static const char *me_bios_path_values[] = {
+static const char *me_bios_path_values[] __unused = {
 	[ME_NORMAL_BIOS_PATH]		= "Normal",
 	[ME_S3WAKE_BIOS_PATH]		= "S3 Wake",
 	[ME_ERROR_BIOS_PATH]		= "Error",
@@ -55,7 +51,6 @@ static const char *me_bios_path_values[] = {
 	[ME_DISABLE_BIOS_PATH]		= "Disable",
 	[ME_FIRMWARE_UPDATE_BIOS_PATH]	= "Firmware Update",
 };
-#endif
 
 /* MMIO base address for MEI interface */
 static u32 *mei_base_address;
@@ -112,7 +107,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
 	mei_dump(ptr, dword, offset, "WRITE");
 }
 
-#ifndef __SMM__
+#ifndef __SIMPLE_DEVICE__
 static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
 {
 	u32 dword = pci_read_config32(dev, offset);
@@ -346,9 +341,8 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
 	return 0;
 }
 
-#ifdef __SMM__
 /* Send END OF POST message to the ME */
-static int mkhi_end_of_post(void)
+static int __unused mkhi_end_of_post(void)
 {
 	struct mkhi_header mkhi = {
 		.group_id	= MKHI_GROUP_ID_GEN,
@@ -370,7 +364,6 @@ static int mkhi_end_of_post(void)
 	printk(BIOS_INFO, "ME: END OF POST message successful\n");
 	return 0;
 }
-#endif
 
 /* Get ME firmware version */
 static int __unused mkhi_get_fw_version(void)
@@ -486,7 +479,8 @@ int mkhi_global_reset(void)
 }
 #endif
 
-#ifdef __SMM__
+#ifdef __SIMPLE_DEVICE__
+
 static void intel_me7_finalize_smm(void)
 {
 	struct me_hfs hfs;
@@ -536,7 +530,8 @@ void intel_me_finalize_smm(void)
 		printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did);
 	}
 }
-#else /* !__SMM__ */
+
+#else
 
 /* Determine the path that we should take based on ME status */
 static me_bios_path intel_me_path(struct device *dev)
@@ -748,4 +743,4 @@ static const struct pci_driver intel_me __pci_driver = {
 	.device	= 0x1c3a,
 };
 
-#endif /* !__SMM__ */
+#endif /* __SIMPLE_DEVICE__ */
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 7af969517d..f13ced939a 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -24,6 +24,8 @@
 
 #include <arch/acpi.h>
 #include <device/mmio.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
@@ -33,11 +35,6 @@
 #include <elog.h>
 #include <halt.h>
 
-#ifndef __SMM__
-#include <device/device.h>
-#include <device/pci.h>
-#endif
-
 #include "me.h"
 #include "pch.h"
 
@@ -46,9 +43,8 @@
 #include <vendorcode/google/chromeos/gnvs.h>
 #endif
 
-#ifndef __SMM__
 /* Path that the BIOS should take based on ME state */
-static const char *me_bios_path_values[] = {
+static const char *me_bios_path_values[] __unused  = {
 	[ME_NORMAL_BIOS_PATH]		= "Normal",
 	[ME_S3WAKE_BIOS_PATH]		= "S3 Wake",
 	[ME_ERROR_BIOS_PATH]		= "Error",
@@ -57,7 +53,6 @@ static const char *me_bios_path_values[] = {
 	[ME_FIRMWARE_UPDATE_BIOS_PATH]	= "Firmware Update",
 };
 static int intel_me_read_mbp(me_bios_payload *mbp_data);
-#endif
 
 /* MMIO base address for MEI interface */
 static u32 *mei_base_address;
@@ -115,7 +110,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
 	mei_dump(ptr, dword, offset, "WRITE");
 }
 
-#ifndef __SMM__
+#ifndef __SIMPLE_DEVICE__
 static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
 {
 	u32 dword = pci_read_config32(dev, offset);
@@ -453,10 +448,8 @@ static int mkhi_global_reset(void)
 }
 #endif
 
-#ifdef __SMM__
-
 /* Send END OF POST message to the ME */
-static int mkhi_end_of_post(void)
+static int __unused mkhi_end_of_post(void)
 {
 	struct mkhi_header mkhi = {
 		.group_id	= MKHI_GROUP_ID_GEN,
@@ -482,6 +475,8 @@ static int mkhi_end_of_post(void)
 	return 0;
 }
 
+#ifdef __SIMPLE_DEVICE__
+
 void intel_me8_finalize_smm(void)
 {
 	struct me_hfs hfs;
@@ -517,7 +512,7 @@ void intel_me8_finalize_smm(void)
 	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
 }
 
-#else /* !__SMM__ */
+#else /* !__SIMPLE_DEVICE__ */
 
 /* Determine the path that we should take based on ME status */
 static me_bios_path intel_me_path(struct device *dev)
@@ -752,6 +747,8 @@ static const struct pci_driver intel_me __pci_driver = {
 	.device	= 0x1e3a,
 };
 
+#endif /* !__SIMPLE_DEVICE__ */
+
 /******************************************************************************
  *									     */
 static u32 me_to_host_words_pending(void)
@@ -783,7 +780,7 @@ static u32 host_to_me_words_room(void)
  * mbp seems to be following its own flow, let's retrieve it in a dedicated
  * function.
  */
-static int intel_me_read_mbp(me_bios_payload *mbp_data)
+static int __unused intel_me_read_mbp(me_bios_payload *mbp_data)
 {
 	mbp_header mbp_hdr;
 	mbp_item_header	mbp_item_hdr;
@@ -907,5 +904,3 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 
 	return 0;
 }
-
-#endif /* !__SMM__ */
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index de7fc36ef6..3cd39a6706 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -17,12 +17,9 @@
 
 #include <console/console.h>
 #include <delay.h>
-#ifdef __SMM__
-#include <device/pci_def.h>
-#else /* !__SMM__ */
 #include <device/device.h>
 #include <device/pci.h>
-#endif
+#include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <string.h>
 
@@ -145,7 +142,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
 		return;
 }
 
-#ifndef __SMM__
+#ifndef __SIMPLE_DEVICE__
 /* Set bit in function disable register to hide this device */
 static void pch_hide_devfn(unsigned int devfn)
 {