diff options
| author | Bill XIE <persmule@gmail.com> | 2017-08-22 16:26:22 +0800 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-08-30 10:32:00 +0000 |
| commit | d533b16669a3bacb19b2824e6b4bc76a2a18c92a (patch) | |
| tree | 2659ee2c6687da3047fe96699dc69ab5b4054bd8 /src/southbridge/intel/bd82x6x | |
| parent | f9267f9bcdcc98f4c1689de3c573feaee511f13d (diff) | |
sb/intel/*: add option to lockdown chipset on normal boot path
On platforms with a PCH, some registers within host bridge should be
locked down on each normal boot path (done by either coreboot or
payload) and S3 resume (always done by coreboot).
A function to perform such locking is implemented in src/northbridge/
intel/*/finalize.c, and is designed as the handler of an #SMI triggered
with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only
triggered during s3 resume, and not on normal boot path. This problem
has beed discussed in
https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html .
This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/
intel/common/Kconfig is added to control the actual locking, which
depends on several compatibility flags, including
"HAVE_INTEL_CHIPSET_LOCKDOWN".
In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint"
have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected.
The change is only well tested on Sandy Bridge, my Lenovo x230.
Change-Id: I43d4142291c8737b29738c41e8c484328b297b55
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 9 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c24c71c30f..9eb3111661 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -39,6 +39,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select HAVE_INTEL_FIRMWARE select SOUTHBRIDGE_INTEL_COMMON_GPIO select RTC + select HAVE_INTEL_CHIPSET_LOCKDOWN config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index ca26250808..901f71be18 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -829,9 +829,12 @@ static void southbridge_fill_ssdt(device_t device) static void lpc_final(struct device *dev) { - if (CONFIG_HAVE_SMI_HANDLER && acpi_is_wakeup_s3()) { - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); + /* Call SMM finalize() handlers before resume */ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) || + acpi_is_wakeup_s3()) { + outb(APM_CNT_FINALIZE, APM_CNT); + } } } |