x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

11 files changed, 302 insertions, 281 deletions

diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index bef88abea4..32223c2c34 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -35,7 +35,7 @@
 
 typedef struct southbridge_intel_bd82x6x_config config_t;
 
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
 {
 	u32 reg32;
 	int count;
@@ -64,7 +64,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
 	return 0;
 }
 
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
 {
 	u8 reg8;
 
@@ -73,7 +73,8 @@ static int codec_detect(u32 base)
 		goto no_codec;
 
 	/* Write back the value once reset bit is set. */
-	write16(base + 0x0, read16(base + 0x0));
+	write16(base + 0x0,
+		read16(base + 0x0));
 
 	/* Read in Codec location (BAR + 0xe)[2..0]*/
 	reg8 = read8(base + 0xe);
@@ -114,14 +115,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
  *  no response would imply that the codec is non-operative
  */
 
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
 {
 	/* Use a 1msec timeout */
 
 	int timeout = 1000;
 
 	while(timeout--) {
-		u32 reg32 = read32(base +  HDA_ICII_REG);
+		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
 		udelay(1);
@@ -136,7 +137,7 @@ static int wait_for_ready(u32 base)
  *  is non-operative
  */
 
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
 {
 	u32 reg32;
 
@@ -159,7 +160,7 @@ static int wait_for_valid(u32 base)
 	return -1;
 }
 
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
 {
 	u32 reg32;
 	const u32 *verb;
@@ -207,7 +208,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
 	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
 }
 
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
 {
 	int i;
 	for (i = 3; i >= 0; i--) {
@@ -228,7 +229,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
 
 static void azalia_init(struct device *dev)
 {
-	u32 base;
+	u8 *base;
 	struct resource *res;
 	u32 codec_mask;
 	u8 reg8;
@@ -242,7 +243,7 @@ static void azalia_init(struct device *dev)
 
 	// NOTE this will break as soon as the Azalia get's a bar above
 	// 4G. Is there anything we can do about it?
-	base = (u32)res->base;
+	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
 
 	if (RCBA32(0x2030) & (1 << 31)) {
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index b1b53af3ad..52c21728e6 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -53,7 +53,7 @@ static void enable_port80_on_lpc(void)
 	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
 
 	/* Enable port 80 POST on LPC */
-	pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
+	pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 #if 0
 	RCBA32(GCS) &= (~0x04);
 #else
diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c
index 0863f3462c..5f4272890a 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_native.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_native.c
@@ -37,7 +37,7 @@
 static void
 wait_2338 (void)
 {
-	while (read8 (DEFAULT_RCBA | 0x2338) & 1);
+	while (read8 (DEFAULT_RCBA + 0x2338) & 1);
 }
 
 static u32
@@ -45,13 +45,13 @@ read_2338 (u32 edx)
 {
 	u32 ret;
 
-	write32 (DEFAULT_RCBA | 0x2330, edx);
-	write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
+	write32 (DEFAULT_RCBA + 0x2330, edx);
+	write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
 					 & 0x1ff) | 0x600);
 	wait_2338 ();
-	ret = read32 (DEFAULT_RCBA | 0x2334);
+	ret = read32 (DEFAULT_RCBA + 0x2334);
 	wait_2338 ();
-	read8 (DEFAULT_RCBA | 0x2338);
+	read8 (DEFAULT_RCBA + 0x2338);
 	return ret;
 }
 
@@ -59,15 +59,15 @@ static void
 write_2338 (u32 edx, u32 val)
 {
 	read_2338 (edx);
-	write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
+	write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
 					 & 0x1ff) | 0x600);
 	wait_2338 ();
 
-	write32 (DEFAULT_RCBA | 0x2334, val);
+	write32 (DEFAULT_RCBA + 0x2334, val);
 	wait_2338 ();
-	write16 (DEFAULT_RCBA | 0x2338,
-		 (read16 (DEFAULT_RCBA | 0x2338) & 0x1ff) | 0x600);
-	read8 (DEFAULT_RCBA | 0x2338);
+	write16 (DEFAULT_RCBA + 0x2338,
+		 (read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600);
+	read8 (DEFAULT_RCBA + 0x2338);
 }
 
 
@@ -76,214 +76,214 @@ init_dmi (void)
 {
 	int i;
 
-	write32 (DEFAULT_DMIBAR | 0x0914,
-		 read32 (DEFAULT_DMIBAR | 0x0914) | 0x80000000);
-	write32 (DEFAULT_DMIBAR | 0x0934,
-		 read32 (DEFAULT_DMIBAR | 0x0934) | 0x80000000);
+	write32 (DEFAULT_DMIBAR + 0x0914,
+		 read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000);
+	write32 (DEFAULT_DMIBAR + 0x0934,
+		 read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000);
 	for (i = 0; i < 4; i++)
 	{
-		write32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4),
-			 read32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4)) & 0xf3ffffff);
-		write32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4),
-			 read32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4)) | 0x800);
+		write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4),
+			 read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff);
+		write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4),
+			 read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800);
 	}
-	write32 (DEFAULT_DMIBAR | 0x0c30, (read32 (DEFAULT_DMIBAR | 0x0c30)
+	write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30)
 					   & 0xfffffff) | 0x40000000);
 	for (i = 0; i < 2; i++)
 	{
-		write32 (DEFAULT_DMIBAR | 0x0904 | (i << 5),
-			 read32 (DEFAULT_DMIBAR | 0x0904 | (i << 5)) & 0xfe3fffff);
-		write32 (DEFAULT_DMIBAR | 0x090c | (i << 5),
-			 read32 (DEFAULT_DMIBAR | 0x090c | (i << 5)) & 0xfff1ffff);
+		write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5),
+			 read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff);
+		write32 (DEFAULT_DMIBAR + 0x090c + (i << 5),
+			 read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff);
 	}
-	write32 (DEFAULT_DMIBAR | 0x090c,
-		 read32 (DEFAULT_DMIBAR | 0x090c) & 0xfe1fffff);
-	write32 (DEFAULT_DMIBAR | 0x092c,
-		 read32 (DEFAULT_DMIBAR | 0x092c) & 0xfe1fffff);
-	read32 (DEFAULT_DMIBAR | 0x0904);	// !!! = 0x7a1842ec
-	write32 (DEFAULT_DMIBAR | 0x0904, 0x7a1842ec);
-	read32 (DEFAULT_DMIBAR | 0x090c);	// !!! = 0x00000208
-	write32 (DEFAULT_DMIBAR | 0x090c, 0x00000128);
-	read32 (DEFAULT_DMIBAR | 0x0924);	// !!! = 0x7a1842ec
-	write32 (DEFAULT_DMIBAR | 0x0924, 0x7a1842ec);
-	read32 (DEFAULT_DMIBAR | 0x092c);	// !!! = 0x00000208
-	write32 (DEFAULT_DMIBAR | 0x092c, 0x00000128);
-	read32 (DEFAULT_DMIBAR | 0x0700);	// !!! = 0x46139008
-	write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
-	read32 (DEFAULT_DMIBAR | 0x0720);	// !!! = 0x46139008
-	write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
-	read32 (DEFAULT_DMIBAR | 0x0c04);	// !!! = 0x2e680008
-	write32 (DEFAULT_DMIBAR | 0x0c04, 0x2e680008);
-	read32 (DEFAULT_DMIBAR | 0x0904);	// !!! = 0x7a1842ec
-	write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1842ec);
-	read32 (DEFAULT_DMIBAR | 0x0924);	// !!! = 0x7a1842ec
-	write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1842ec);
-	read32 (DEFAULT_DMIBAR | 0x0910);	// !!! = 0x00006300
-	write32 (DEFAULT_DMIBAR | 0x0910, 0x00004300);
-	read32 (DEFAULT_DMIBAR | 0x0930);	// !!! = 0x00006300
-	write32 (DEFAULT_DMIBAR | 0x0930, 0x00004300);
-	read32 (DEFAULT_DMIBAR | 0x0a00);	// !!! = 0x03042010
-	write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a10);	// !!! = 0x03042010
-	write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a20);	// !!! = 0x03042010
-	write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a30);	// !!! = 0x03042010
-	write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0c00);	// !!! = 0x29700c08
-	write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
-	read32 (DEFAULT_DMIBAR | 0x0a04);	// !!! = 0x0c0708f0
-	write32 (DEFAULT_DMIBAR | 0x0a04, 0x0c0718f0);
-	read32 (DEFAULT_DMIBAR | 0x0a14);	// !!! = 0x0c0708f0
-	write32 (DEFAULT_DMIBAR | 0x0a14, 0x0c0718f0);
-	read32 (DEFAULT_DMIBAR | 0x0a24);	// !!! = 0x0c0708f0
-	write32 (DEFAULT_DMIBAR | 0x0a24, 0x0c0718f0);
-	read32 (DEFAULT_DMIBAR | 0x0a34);	// !!! = 0x0c0708f0
-	write32 (DEFAULT_DMIBAR | 0x0a34, 0x0c0718f0);
-	read32 (DEFAULT_DMIBAR | 0x0900);	// !!! = 0x50000000
-	write32 (DEFAULT_DMIBAR | 0x0900, 0x50000000);
-	read32 (DEFAULT_DMIBAR | 0x0920);	// !!! = 0x50000000
-	write32 (DEFAULT_DMIBAR | 0x0920, 0x50000000);
-	read32 (DEFAULT_DMIBAR | 0x0908);	// !!! = 0x51ffffff
-	write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
-	read32 (DEFAULT_DMIBAR | 0x0928);	// !!! = 0x51ffffff
-	write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
-	read32 (DEFAULT_DMIBAR | 0x0a00);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a10);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a20);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a30);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0700);	// !!! = 0x46139008
-	write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
-	read32 (DEFAULT_DMIBAR | 0x0720);	// !!! = 0x46139008
-	write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
-	read32 (DEFAULT_DMIBAR | 0x0904);	// !!! = 0x3a1842ec
-	write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1846ec);
-	read32 (DEFAULT_DMIBAR | 0x0924);	// !!! = 0x3a1842ec
-	write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1846ec);
-	read32 (DEFAULT_DMIBAR | 0x0a00);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a10);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a20);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0a30);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
-	read32 (DEFAULT_DMIBAR | 0x0908);	// !!! = 0x51ffffff
-	write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
-	read32 (DEFAULT_DMIBAR | 0x0928);	// !!! = 0x51ffffff
-	write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
-	read32 (DEFAULT_DMIBAR | 0x0c00);	// !!! = 0x29700c08
-	write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
-	read32 (DEFAULT_DMIBAR | 0x0c0c);	// !!! = 0x16063400
-	write32 (DEFAULT_DMIBAR | 0x0c0c, 0x00063400);
-	read32 (DEFAULT_DMIBAR | 0x0700);	// !!! = 0x46139008
-	write32 (DEFAULT_DMIBAR | 0x0700, 0x46339008);
-	read32 (DEFAULT_DMIBAR | 0x0720);	// !!! = 0x46139008
-	write32 (DEFAULT_DMIBAR | 0x0720, 0x46339008);
-	read32 (DEFAULT_DMIBAR | 0x0700);	// !!! = 0x46339008
-	write32 (DEFAULT_DMIBAR | 0x0700, 0x45339008);
-	read32 (DEFAULT_DMIBAR | 0x0720);	// !!! = 0x46339008
-	write32 (DEFAULT_DMIBAR | 0x0720, 0x45339008);
-	read32 (DEFAULT_DMIBAR | 0x0700);	// !!! = 0x45339008
-	write32 (DEFAULT_DMIBAR | 0x0700, 0x453b9008);
-	read32 (DEFAULT_DMIBAR | 0x0720);	// !!! = 0x45339008
-	write32 (DEFAULT_DMIBAR | 0x0720, 0x453b9008);
-	read32 (DEFAULT_DMIBAR | 0x0700);	// !!! = 0x453b9008
-	write32 (DEFAULT_DMIBAR | 0x0700, 0x45bb9008);
-	read32 (DEFAULT_DMIBAR | 0x0720);	// !!! = 0x453b9008
-	write32 (DEFAULT_DMIBAR | 0x0720, 0x45bb9008);
-	read32 (DEFAULT_DMIBAR | 0x0700);	// !!! = 0x45bb9008
-	write32 (DEFAULT_DMIBAR | 0x0700, 0x45fb9008);
-	read32 (DEFAULT_DMIBAR | 0x0720);	// !!! = 0x45bb9008
-	write32 (DEFAULT_DMIBAR | 0x0720, 0x45fb9008);
-	read32 (DEFAULT_DMIBAR | 0x0914);	// !!! = 0x9021a080
-	write32 (DEFAULT_DMIBAR | 0x0914, 0x9021a280);
-	read32 (DEFAULT_DMIBAR | 0x0934);	// !!! = 0x9021a080
-	write32 (DEFAULT_DMIBAR | 0x0934, 0x9021a280);
-	read32 (DEFAULT_DMIBAR | 0x0914);	// !!! = 0x9021a280
-	write32 (DEFAULT_DMIBAR | 0x0914, 0x9821a280);
-	read32 (DEFAULT_DMIBAR | 0x0934);	// !!! = 0x9021a280
-	write32 (DEFAULT_DMIBAR | 0x0934, 0x9821a280);
-	read32 (DEFAULT_DMIBAR | 0x0a00);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a00, 0x03242018);
-	read32 (DEFAULT_DMIBAR | 0x0a10);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a10, 0x03242018);
-	read32 (DEFAULT_DMIBAR | 0x0a20);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a20, 0x03242018);
-	read32 (DEFAULT_DMIBAR | 0x0a30);	// !!! = 0x03042018
-	write32 (DEFAULT_DMIBAR | 0x0a30, 0x03242018);
-	read32 (DEFAULT_DMIBAR | 0x0258);	// !!! = 0x40000600
-	write32 (DEFAULT_DMIBAR | 0x0258, 0x60000600);
-	read32 (DEFAULT_DMIBAR | 0x0904);	// !!! = 0x3a1846ec
-	write32 (DEFAULT_DMIBAR | 0x0904, 0x2a1846ec);
-	read32 (DEFAULT_DMIBAR | 0x0914);	// !!! = 0x9821a280
-	write32 (DEFAULT_DMIBAR | 0x0914, 0x98200280);
-	read32 (DEFAULT_DMIBAR | 0x0924);	// !!! = 0x3a1846ec
-	write32 (DEFAULT_DMIBAR | 0x0924, 0x2a1846ec);
-	read32 (DEFAULT_DMIBAR | 0x0934);	// !!! = 0x9821a280
-	write32 (DEFAULT_DMIBAR | 0x0934, 0x98200280);
-	read32 (DEFAULT_DMIBAR | 0x022c);	// !!! = 0x00c26460
-	write32 (DEFAULT_DMIBAR | 0x022c, 0x00c2403c);
-	read8 (DEFAULT_RCBA | 0x21a4);	// !!! = 0x42
+	write32 (DEFAULT_DMIBAR + 0x090c,
+		 read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff);
+	write32 (DEFAULT_DMIBAR + 0x092c,
+		 read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff);
+	read32 (DEFAULT_DMIBAR + 0x0904);	// !!! = 0x7a1842ec
+	write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec);
+	read32 (DEFAULT_DMIBAR + 0x090c);	// !!! = 0x00000208
+	write32 (DEFAULT_DMIBAR + 0x090c, 0x00000128);
+	read32 (DEFAULT_DMIBAR + 0x0924);	// !!! = 0x7a1842ec
+	write32 (DEFAULT_DMIBAR + 0x0924, 0x7a1842ec);
+	read32 (DEFAULT_DMIBAR + 0x092c);	// !!! = 0x00000208
+	write32 (DEFAULT_DMIBAR + 0x092c, 0x00000128);
+	read32 (DEFAULT_DMIBAR + 0x0700);	// !!! = 0x46139008
+	write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008);
+	read32 (DEFAULT_DMIBAR + 0x0720);	// !!! = 0x46139008
+	write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008);
+	read32 (DEFAULT_DMIBAR + 0x0c04);	// !!! = 0x2e680008
+	write32 (DEFAULT_DMIBAR + 0x0c04, 0x2e680008);
+	read32 (DEFAULT_DMIBAR + 0x0904);	// !!! = 0x7a1842ec
+	write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1842ec);
+	read32 (DEFAULT_DMIBAR + 0x0924);	// !!! = 0x7a1842ec
+	write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1842ec);
+	read32 (DEFAULT_DMIBAR + 0x0910);	// !!! = 0x00006300
+	write32 (DEFAULT_DMIBAR + 0x0910, 0x00004300);
+	read32 (DEFAULT_DMIBAR + 0x0930);	// !!! = 0x00006300
+	write32 (DEFAULT_DMIBAR + 0x0930, 0x00004300);
+	read32 (DEFAULT_DMIBAR + 0x0a00);	// !!! = 0x03042010
+	write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a10);	// !!! = 0x03042010
+	write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a20);	// !!! = 0x03042010
+	write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a30);	// !!! = 0x03042010
+	write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0c00);	// !!! = 0x29700c08
+	write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08);
+	read32 (DEFAULT_DMIBAR + 0x0a04);	// !!! = 0x0c0708f0
+	write32 (DEFAULT_DMIBAR + 0x0a04, 0x0c0718f0);
+	read32 (DEFAULT_DMIBAR + 0x0a14);	// !!! = 0x0c0708f0
+	write32 (DEFAULT_DMIBAR + 0x0a14, 0x0c0718f0);
+	read32 (DEFAULT_DMIBAR + 0x0a24);	// !!! = 0x0c0708f0
+	write32 (DEFAULT_DMIBAR + 0x0a24, 0x0c0718f0);
+	read32 (DEFAULT_DMIBAR + 0x0a34);	// !!! = 0x0c0708f0
+	write32 (DEFAULT_DMIBAR + 0x0a34, 0x0c0718f0);
+	read32 (DEFAULT_DMIBAR + 0x0900);	// !!! = 0x50000000
+	write32 (DEFAULT_DMIBAR + 0x0900, 0x50000000);
+	read32 (DEFAULT_DMIBAR + 0x0920);	// !!! = 0x50000000
+	write32 (DEFAULT_DMIBAR + 0x0920, 0x50000000);
+	read32 (DEFAULT_DMIBAR + 0x0908);	// !!! = 0x51ffffff
+	write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff);
+	read32 (DEFAULT_DMIBAR + 0x0928);	// !!! = 0x51ffffff
+	write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff);
+	read32 (DEFAULT_DMIBAR + 0x0a00);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a10);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a20);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a30);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0700);	// !!! = 0x46139008
+	write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008);
+	read32 (DEFAULT_DMIBAR + 0x0720);	// !!! = 0x46139008
+	write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008);
+	read32 (DEFAULT_DMIBAR + 0x0904);	// !!! = 0x3a1842ec
+	write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1846ec);
+	read32 (DEFAULT_DMIBAR + 0x0924);	// !!! = 0x3a1842ec
+	write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1846ec);
+	read32 (DEFAULT_DMIBAR + 0x0a00);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a10);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a20);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0a30);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
+	read32 (DEFAULT_DMIBAR + 0x0908);	// !!! = 0x51ffffff
+	write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff);
+	read32 (DEFAULT_DMIBAR + 0x0928);	// !!! = 0x51ffffff
+	write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff);
+	read32 (DEFAULT_DMIBAR + 0x0c00);	// !!! = 0x29700c08
+	write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08);
+	read32 (DEFAULT_DMIBAR + 0x0c0c);	// !!! = 0x16063400
+	write32 (DEFAULT_DMIBAR + 0x0c0c, 0x00063400);
+	read32 (DEFAULT_DMIBAR + 0x0700);	// !!! = 0x46139008
+	write32 (DEFAULT_DMIBAR + 0x0700, 0x46339008);
+	read32 (DEFAULT_DMIBAR + 0x0720);	// !!! = 0x46139008
+	write32 (DEFAULT_DMIBAR + 0x0720, 0x46339008);
+	read32 (DEFAULT_DMIBAR + 0x0700);	// !!! = 0x46339008
+	write32 (DEFAULT_DMIBAR + 0x0700, 0x45339008);
+	read32 (DEFAULT_DMIBAR + 0x0720);	// !!! = 0x46339008
+	write32 (DEFAULT_DMIBAR + 0x0720, 0x45339008);
+	read32 (DEFAULT_DMIBAR + 0x0700);	// !!! = 0x45339008
+	write32 (DEFAULT_DMIBAR + 0x0700, 0x453b9008);
+	read32 (DEFAULT_DMIBAR + 0x0720);	// !!! = 0x45339008
+	write32 (DEFAULT_DMIBAR + 0x0720, 0x453b9008);
+	read32 (DEFAULT_DMIBAR + 0x0700);	// !!! = 0x453b9008
+	write32 (DEFAULT_DMIBAR + 0x0700, 0x45bb9008);
+	read32 (DEFAULT_DMIBAR + 0x0720);	// !!! = 0x453b9008
+	write32 (DEFAULT_DMIBAR + 0x0720, 0x45bb9008);
+	read32 (DEFAULT_DMIBAR + 0x0700);	// !!! = 0x45bb9008
+	write32 (DEFAULT_DMIBAR + 0x0700, 0x45fb9008);
+	read32 (DEFAULT_DMIBAR + 0x0720);	// !!! = 0x45bb9008
+	write32 (DEFAULT_DMIBAR + 0x0720, 0x45fb9008);
+	read32 (DEFAULT_DMIBAR + 0x0914);	// !!! = 0x9021a080
+	write32 (DEFAULT_DMIBAR + 0x0914, 0x9021a280);
+	read32 (DEFAULT_DMIBAR + 0x0934);	// !!! = 0x9021a080
+	write32 (DEFAULT_DMIBAR + 0x0934, 0x9021a280);
+	read32 (DEFAULT_DMIBAR + 0x0914);	// !!! = 0x9021a280
+	write32 (DEFAULT_DMIBAR + 0x0914, 0x9821a280);
+	read32 (DEFAULT_DMIBAR + 0x0934);	// !!! = 0x9021a280
+	write32 (DEFAULT_DMIBAR + 0x0934, 0x9821a280);
+	read32 (DEFAULT_DMIBAR + 0x0a00);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a00, 0x03242018);
+	read32 (DEFAULT_DMIBAR + 0x0a10);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a10, 0x03242018);
+	read32 (DEFAULT_DMIBAR + 0x0a20);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a20, 0x03242018);
+	read32 (DEFAULT_DMIBAR + 0x0a30);	// !!! = 0x03042018
+	write32 (DEFAULT_DMIBAR + 0x0a30, 0x03242018);
+	read32 (DEFAULT_DMIBAR + 0x0258);	// !!! = 0x40000600
+	write32 (DEFAULT_DMIBAR + 0x0258, 0x60000600);
+	read32 (DEFAULT_DMIBAR + 0x0904);	// !!! = 0x3a1846ec
+	write32 (DEFAULT_DMIBAR + 0x0904, 0x2a1846ec);
+	read32 (DEFAULT_DMIBAR + 0x0914);	// !!! = 0x9821a280
+	write32 (DEFAULT_DMIBAR + 0x0914, 0x98200280);
+	read32 (DEFAULT_DMIBAR + 0x0924);	// !!! = 0x3a1846ec
+	write32 (DEFAULT_DMIBAR + 0x0924, 0x2a1846ec);
+	read32 (DEFAULT_DMIBAR + 0x0934);	// !!! = 0x9821a280
+	write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280);
+	read32 (DEFAULT_DMIBAR + 0x022c);	// !!! = 0x00c26460
+	write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c);
+	read8 (DEFAULT_RCBA + 0x21a4);	// !!! = 0x42
 
-	read32 (DEFAULT_RCBA | 0x21a4);	// !!! = 0x00012c42
-	read32 (DEFAULT_RCBA | 0x2340);	// !!! = 0x0013001b
-	write32 (DEFAULT_RCBA | 0x2340, 0x003a001b);
-	read8 (DEFAULT_RCBA | 0x21b0);	// !!! = 0x01
-	write8 (DEFAULT_RCBA | 0x21b0, 0x02);
-	read32 (DEFAULT_DMIBAR | 0x0084);	// !!! = 0x0041ac41
-	write32 (DEFAULT_DMIBAR | 0x0084, 0x0041ac42);
-	read8 (DEFAULT_DMIBAR | 0x0088);	// !!! = 0x00
-	write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
-	read16 (DEFAULT_DMIBAR | 0x008a);	// !!! = 0x0041
-	read8 (DEFAULT_DMIBAR | 0x0088);	// !!! = 0x00
-	write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
-	read16 (DEFAULT_DMIBAR | 0x008a);	// !!! = 0x0042
-	read16 (DEFAULT_DMIBAR | 0x008a);	// !!! = 0x0042
+	read32 (DEFAULT_RCBA + 0x21a4);	// !!! = 0x00012c42
+	read32 (DEFAULT_RCBA + 0x2340);	// !!! = 0x0013001b
+	write32 (DEFAULT_RCBA + 0x2340, 0x003a001b);
+	read8 (DEFAULT_RCBA + 0x21b0);	// !!! = 0x01
+	write8 (DEFAULT_RCBA + 0x21b0, 0x02);
+	read32 (DEFAULT_DMIBAR + 0x0084);	// !!! = 0x0041ac41
+	write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42);
+	read8 (DEFAULT_DMIBAR + 0x0088);	// !!! = 0x00
+	write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
+	read16 (DEFAULT_DMIBAR + 0x008a);	// !!! = 0x0041
+	read8 (DEFAULT_DMIBAR + 0x0088);	// !!! = 0x00
+	write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
+	read16 (DEFAULT_DMIBAR + 0x008a);	// !!! = 0x0042
+	read16 (DEFAULT_DMIBAR + 0x008a);	// !!! = 0x0042
 
-	read32 (DEFAULT_DMIBAR | 0x0014);	// !!! = 0x8000007f
-	write32 (DEFAULT_DMIBAR | 0x0014, 0x80000019);
-	read32 (DEFAULT_DMIBAR | 0x0020);	// !!! = 0x01000000
-	write32 (DEFAULT_DMIBAR | 0x0020, 0x81000022);
-	read32 (DEFAULT_DMIBAR | 0x002c);	// !!! = 0x02000000
-	write32 (DEFAULT_DMIBAR | 0x002c, 0x82000044);
-	read32 (DEFAULT_DMIBAR | 0x0038);	// !!! = 0x07000080
-	write32 (DEFAULT_DMIBAR | 0x0038, 0x87000080);
-	read8 (DEFAULT_DMIBAR | 0x0004);	// !!! = 0x00
-	write8 (DEFAULT_DMIBAR | 0x0004, 0x01);
+	read32 (DEFAULT_DMIBAR + 0x0014);	// !!! = 0x8000007f
+	write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019);
+	read32 (DEFAULT_DMIBAR + 0x0020);	// !!! = 0x01000000
+	write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022);
+	read32 (DEFAULT_DMIBAR + 0x002c);	// !!! = 0x02000000
+	write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044);
+	read32 (DEFAULT_DMIBAR + 0x0038);	// !!! = 0x07000080
+	write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080);
+	read8 (DEFAULT_DMIBAR + 0x0004);	// !!! = 0x00
+	write8 (DEFAULT_DMIBAR + 0x0004, 0x01);
 
-	read32 (DEFAULT_RCBA | 0x0050);	// !!! = 0x01200654
-	write32 (DEFAULT_RCBA | 0x0050, 0x01200654);
-	read32 (DEFAULT_RCBA | 0x0050);	// !!! = 0x01200654
-	write32 (DEFAULT_RCBA | 0x0050, 0x012a0654);
-	read32 (DEFAULT_RCBA | 0x0050);	// !!! = 0x012a0654
-	read8 (DEFAULT_RCBA | 0x1114);	// !!! = 0x00
-	write8 (DEFAULT_RCBA | 0x1114, 0x05);
-	read32 (DEFAULT_RCBA | 0x2014);	// !!! = 0x80000011
-	write32 (DEFAULT_RCBA | 0x2014, 0x80000019);
-	read32 (DEFAULT_RCBA | 0x2020);	// !!! = 0x00000000
-	write32 (DEFAULT_RCBA | 0x2020, 0x81000022);
-	read32 (DEFAULT_RCBA | 0x2020);	// !!! = 0x81000022
-	read32 (DEFAULT_RCBA | 0x2030);	// !!! = 0x00000000
-	write32 (DEFAULT_RCBA | 0x2030, 0x82000044);
-	read32 (DEFAULT_RCBA | 0x2030);	// !!! = 0x82000044
-	read32 (DEFAULT_RCBA | 0x2040);	// !!! = 0x00000000
-	write32 (DEFAULT_RCBA | 0x2040, 0x87000080);
-	read32 (DEFAULT_RCBA | 0x0050);	// !!! = 0x012a0654
-	write32 (DEFAULT_RCBA | 0x0050, 0x812a0654);
-	read32 (DEFAULT_RCBA | 0x0050);	// !!! = 0x812a0654
-	read16 (DEFAULT_RCBA | 0x201a);	// !!! = 0x0000
-	read16 (DEFAULT_RCBA | 0x2026);	// !!! = 0x0000
-	read16 (DEFAULT_RCBA | 0x2036);	// !!! = 0x0000
-	read16 (DEFAULT_RCBA | 0x2046);	// !!! = 0x0000
-	read16 (DEFAULT_DMIBAR | 0x001a);	// !!! = 0x0000
-	read16 (DEFAULT_DMIBAR | 0x0026);	// !!! = 0x0000
-	read16 (DEFAULT_DMIBAR | 0x0032);	// !!! = 0x0000
-	read16 (DEFAULT_DMIBAR | 0x003e);	// !!! = 0x0000
+	read32 (DEFAULT_RCBA + 0x0050);	// !!! = 0x01200654
+	write32 (DEFAULT_RCBA + 0x0050, 0x01200654);
+	read32 (DEFAULT_RCBA + 0x0050);	// !!! = 0x01200654
+	write32 (DEFAULT_RCBA + 0x0050, 0x012a0654);
+	read32 (DEFAULT_RCBA + 0x0050);	// !!! = 0x012a0654
+	read8 (DEFAULT_RCBA + 0x1114);	// !!! = 0x00
+	write8 (DEFAULT_RCBA + 0x1114, 0x05);
+	read32 (DEFAULT_RCBA + 0x2014);	// !!! = 0x80000011
+	write32 (DEFAULT_RCBA + 0x2014, 0x80000019);
+	read32 (DEFAULT_RCBA + 0x2020);	// !!! = 0x00000000
+	write32 (DEFAULT_RCBA + 0x2020, 0x81000022);
+	read32 (DEFAULT_RCBA + 0x2020);	// !!! = 0x81000022
+	read32 (DEFAULT_RCBA + 0x2030);	// !!! = 0x00000000
+	write32 (DEFAULT_RCBA + 0x2030, 0x82000044);
+	read32 (DEFAULT_RCBA + 0x2030);	// !!! = 0x82000044
+	read32 (DEFAULT_RCBA + 0x2040);	// !!! = 0x00000000
+	write32 (DEFAULT_RCBA + 0x2040, 0x87000080);
+	read32 (DEFAULT_RCBA + 0x0050);	// !!! = 0x012a0654
+	write32 (DEFAULT_RCBA + 0x0050, 0x812a0654);
+	read32 (DEFAULT_RCBA + 0x0050);	// !!! = 0x812a0654
+	read16 (DEFAULT_RCBA + 0x201a);	// !!! = 0x0000
+	read16 (DEFAULT_RCBA + 0x2026);	// !!! = 0x0000
+	read16 (DEFAULT_RCBA + 0x2036);	// !!! = 0x0000
+	read16 (DEFAULT_RCBA + 0x2046);	// !!! = 0x0000
+	read16 (DEFAULT_DMIBAR + 0x001a);	// !!! = 0x0000
+	read16 (DEFAULT_DMIBAR + 0x0026);	// !!! = 0x0000
+	read16 (DEFAULT_DMIBAR + 0x0032);	// !!! = 0x0000
+	read16 (DEFAULT_DMIBAR + 0x003e);	// !!! = 0x0000
 }
 
 void
@@ -292,21 +292,21 @@ early_pch_init_native (void)
 	pcie_write_config8 (SOUTHBRIDGE, 0xa6,
 			    pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
 
-	write32 (DEFAULT_RCBA | 0x2088, 0x00109000);
-	read32 (DEFAULT_RCBA | 0x20ac);	// !!! = 0x00000000
-	write32 (DEFAULT_RCBA | 0x20ac, 0x40000000);
-	write32 (DEFAULT_RCBA | 0x100c, 0x01110000);
-	write8 (DEFAULT_RCBA | 0x2340, 0x1b);
-	read32 (DEFAULT_RCBA | 0x2314);	// !!! = 0x0a080000
-	write32 (DEFAULT_RCBA | 0x2314, 0x0a280000);
-	read32 (DEFAULT_RCBA | 0x2310);	// !!! = 0xc809605b
-	write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
-	write32 (DEFAULT_RCBA | 0x2324, 0x00854c74);
-	read8 (DEFAULT_RCBA | 0x0400);	// !!! = 0x00
-	read32 (DEFAULT_RCBA | 0x2310);	// !!! = 0xa809605b
-	write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
-	read32 (DEFAULT_RCBA | 0x2310);	// !!! = 0xa809605b
-	write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
+	write32 (DEFAULT_RCBA + 0x2088, 0x00109000);
+	read32 (DEFAULT_RCBA + 0x20ac);	// !!! = 0x00000000
+	write32 (DEFAULT_RCBA + 0x20ac, 0x40000000);
+	write32 (DEFAULT_RCBA + 0x100c, 0x01110000);
+	write8 (DEFAULT_RCBA + 0x2340, 0x1b);
+	read32 (DEFAULT_RCBA + 0x2314);	// !!! = 0x0a080000
+	write32 (DEFAULT_RCBA + 0x2314, 0x0a280000);
+	read32 (DEFAULT_RCBA + 0x2310);	// !!! = 0xc809605b
+	write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
+	write32 (DEFAULT_RCBA + 0x2324, 0x00854c74);
+	read8 (DEFAULT_RCBA + 0x0400);	// !!! = 0x00
+	read32 (DEFAULT_RCBA + 0x2310);	// !!! = 0xa809605b
+	write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
+	read32 (DEFAULT_RCBA + 0x2310);	// !!! = 0xa809605b
+	write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
 
 	write_2338 (0xea007f62, 0x00590133);
 	write_2338 (0xec007f62, 0x00590133);
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index 02ec9a7436..f2d04dd8a8 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -23,6 +23,21 @@
 #include "cpu/intel/model_206ax/model_206ax.h"
 #include <cpu/x86/msr.h>
 
+static void write8p(uintptr_t addr, uint32_t val)
+{
+	write8((u8 *)addr, val);
+}
+
+static void write16p(uintptr_t addr, uint32_t val)
+{
+	write16((u16 *)addr, val);
+}
+
+static uint16_t read16p (uintptr_t addr)
+{
+	return read16((u16 *)addr);
+}
+
 /* Early thermal init, must be done prior to giving ME its memory
    which is done at the end of raminit.  */
 void early_thermal_init(void)
@@ -41,30 +56,30 @@ void early_thermal_init(void)
 			   pci_read_config32(dev, 0x40) | 5);
 
 
-	write16 (0x40000004, 0x3a2b);
-	write8 (0x4000000c, 0xff);
-	write8 (0x4000000d, 0x00);
-	write8 (0x4000000e, 0x40);
-	write8 (0x40000082, 0x00);
-	write8 (0x40000001, 0xba);
+	write16p (0x40000004, 0x3a2b);
+	write8p (0x4000000c, 0xff);
+	write8p (0x4000000d, 0x00);
+	write8p (0x4000000e, 0x40);
+	write8p (0x40000082, 0x00);
+	write8p (0x40000001, 0xba);
 
 	/* Perform init.  */
 	/* Configure TJmax.  */
 	msr = rdmsr(MSR_TEMPERATURE_TARGET);
-	write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
+	write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
 	/* Northbridge temperature slope and offset.  */
-	write16(0x40000016, 0x808c);
+	write16p(0x40000016, 0x808c);
 
-	write16 (0x40000014, 0xde87);
+	write16p (0x40000014, 0xde87);
 
 	/* Enable thermal data reporting, processor, PCH and northbridge.  */
-	write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
+	write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0);
 
 	/* Disable temporary BAR.  */
 	pci_write_config32(dev, 0x40,
 			   pci_read_config32(dev, 0x40) & ~1);
 	pci_write_config32(dev, 0x40, 0);
 
-	write32 (DEFAULT_RCBA | 0x38b0,
-		 (read32 (DEFAULT_RCBA | 0x38b0) & 0xffff8003) | 0x403c);
+	write32 (DEFAULT_RCBA + 0x38b0,
+		 (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
 }
diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c
index b8247c6025..b267f95eb7 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_native.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_native.c
@@ -43,32 +43,32 @@ early_usb_init (const struct southbridge_usb_port *portmap)
 	/* Unlock registers.  */
 	outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
 	for (i = 0; i < 14; i++)
-		write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i),
+		write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i),
 			 currents[portmap[i].current]);
 	for (i = 0; i < 10; i++)
-		write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0);
+		write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0);
 
 	for (i = 0; i < 8; i++)
-		write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]);
+		write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]);
 	for (i = 0; i < 8; i++)
-		write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0);
+		write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0);
 	reg32 = 0;
 	for (i = 0; i < 14; i++)
 		if (!portmap[i].enabled)
 			reg32 |= (1 << i);
-	write32 (DEFAULT_RCBABASE | USBPDO, reg32);
+	write32 (DEFAULT_RCBABASE + USBPDO, reg32);
 	reg32 = 0;
 	for (i = 0; i < 8; i++)
 		if (portmap[i].enabled && portmap[i].oc_pin >= 0)
 			reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
-	write32 (DEFAULT_RCBABASE | USBOCM1, reg32);
+	write32 (DEFAULT_RCBABASE + USBOCM1, reg32);
 	reg32 = 0;
 	for (i = 8; i < 14; i++)
 		if (portmap[i].enabled && portmap[i].oc_pin >= 4)
 			reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
-	write32 (DEFAULT_RCBABASE | USBOCM2, reg32);
+	write32 (DEFAULT_RCBABASE + USBOCM2, reg32);
 	for (i = 0; i < 22; i++)
-		write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0);
+		write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);
 
 	pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
 
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 11b765adc6..c323f738fc 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -59,17 +59,17 @@ static void pch_enable_ioapic(struct device *dev)
 	/* Enable ACPI I/O range decode */
 	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
 
-	set_ioapic_id(IO_APIC_ADDR, 0x02);
+	set_ioapic_id(VIO_APIC_VADDR, 0x02);
 
 	/* affirm full set of redirection table entries ("write once") */
-	reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
-	io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+	reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
+	io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
 
 	/*
 	 * Select Boot Configuration register (0x03) and
 	 * use Processor System Bus (0x01) to deliver interrupts.
 	 */
-	io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+	io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
 }
 
 static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 901e71dd5e..df188308cf 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -64,7 +64,7 @@ static const char *me_bios_path_values[] = {
 #endif
 
 /* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
 
 #if CONFIG_DEBUG_INTEL_ME
 static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
 
 static inline void mei_read_dword_ptr(void *ptr, int offset)
 {
-	u32 dword = read32(mei_base_address + offset);
+	u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
 	memcpy(ptr, &dword, sizeof(dword));
 	mei_dump(ptr, dword, offset, "READ");
 }
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
 {
 	u32 dword = 0;
 	memcpy(&dword, ptr, sizeof(dword));
-	write32(mei_base_address + offset, dword);
+	write32(mei_base_address + (offset/sizeof(u32)), dword);
 	mei_dump(ptr, dword, offset, "WRITE");
 }
 
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
 
 static inline void write_cb(u32 dword)
 {
-	write32(mei_base_address + MEI_H_CB_WW, dword);
+	write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
 	mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
 }
 
 static inline u32 read_cb(void)
 {
-	u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+	u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
 	mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
 	return dword;
 }
@@ -501,11 +501,11 @@ static void intel_me7_finalize_smm(void)
 	struct me_hfs hfs;
 	u32 reg32;
 
-	mei_base_address =
-		pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+	mei_base_address = (u32 *)
+		(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
 
 	/* S3 path will have hidden this device already */
-	if (!mei_base_address || mei_base_address == 0xfffffff0)
+	if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
 		return;
 
 	/* Make sure ME is in a mode that expects EOP */
@@ -627,7 +627,7 @@ static int intel_mei_setup(device_t dev)
 		printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
 		return -1;
 	}
-	mei_base_address = res->base;
+	mei_base_address = (u32*)(uintptr_t)res->base;
 
 	/* Ensure Memory and Bus Master bits are set */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index e25b3b8c4f..3fa326962a 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -66,7 +66,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
 #endif
 
 /* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
 
 #if CONFIG_DEBUG_INTEL_ME
 static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -108,7 +108,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
 
 static inline void mei_read_dword_ptr(void *ptr, int offset)
 {
-	u32 dword = read32(mei_base_address + offset);
+	u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
 	memcpy(ptr, &dword, sizeof(dword));
 	mei_dump(ptr, dword, offset, "READ");
 }
@@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
 {
 	u32 dword = 0;
 	memcpy(&dword, ptr, sizeof(dword));
-	write32(mei_base_address + offset, dword);
+	write32(mei_base_address + (offset/sizeof(u32)), dword);
 	mei_dump(ptr, dword, offset, "WRITE");
 }
 
@@ -147,13 +147,13 @@ static inline void read_me_csr(struct mei_csr *csr)
 
 static inline void write_cb(u32 dword)
 {
-	write32(mei_base_address + MEI_H_CB_WW, dword);
+	write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
 	mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
 }
 
 static inline u32 read_cb(void)
 {
-	u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+	u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
 	mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
 	return dword;
 }
@@ -495,11 +495,11 @@ void intel_me8_finalize_smm(void)
 	struct me_hfs hfs;
 	u32 reg32;
 
-	mei_base_address =
-		pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+	mei_base_address = (void *)
+		(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
 
 	/* S3 path will have hidden this device already */
-	if (!mei_base_address || mei_base_address == 0xfffffff0)
+	if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
 		return;
 
 	/* Make sure ME is in a mode that expects EOP */
@@ -614,7 +614,7 @@ static int intel_mei_setup(device_t dev)
 		printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
 		return -1;
 	}
-	mei_base_address = res->base;
+	mei_base_address = (u32 *)(uintptr_t)res->base;
 
 	/* Ensure Memory and Bus Master bits are set */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index cfdea7c979..029da9fb35 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -47,7 +47,11 @@
 #define DEFAULT_GPIOBASE	0x0480
 #define DEFAULT_PMBASE		0x0500
 
+#ifndef __ACPI__
+#define DEFAULT_RCBA		((u8 *)0xfed1c000)
+#else
 #define DEFAULT_RCBA		0xfed1c000
+#endif
 
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e713..cf3b14ef90 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -66,7 +66,7 @@ static void sata_init(struct device *dev)
 
 	/* AHCI */
 	if (sata_mode == 0) {
-		u32 abar;
+		u8 *abar;
 
 		printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
 
@@ -100,8 +100,8 @@ static void sata_init(struct device *dev)
 			   ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
 
 		/* Initialize AHCI memory-mapped space */
-		abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-		printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+		abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+		printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 		/* CAP (HBA Capabilities) : enable power management */
 		reg32 = read32(abar + 0x00);
 		reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 9850fee30d..b76963fdb1 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -66,8 +66,9 @@ static void usb_ehci_init(struct device *dev)
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (res) {
 		/* Number of ports and companion controllers.  */
-		reg32 = read32(res->base + 4);
-		write32(res->base + 4, (reg32 & 0xfff00000) | 3);
+		reg32 = read32((void *)(uintptr_t)(res->base + 4));
+		write32((void *)(uintptr_t)(res->base + 4),
+			(reg32 & 0xfff00000) | 3);
 	}
 
 	/* Restore protection. */