diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-28 14:27:46 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-06 09:08:15 +0000 |
| commit | b70ff52b83d5ffe9feca95d086a5366dd6f6ce4d (patch) | |
| tree | cb78016240a6c4cd35905230d7f0f807eedbe91e /src/southbridge/intel/bd82x6x | |
| parent | ca935d1107ccc3ba77cc6915360f17f38e2f328d (diff) | |
intel: Define `RCBA_LENGTH` in Kconfig and use it
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 8833a5ed2e..5a80ab0b3e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -181,7 +181,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone |