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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-14 17:46:30 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-17 07:44:25 +0000 |
| commit | 806b2cd42b94b548a5bfa69a7e9c0cf2fda20f7f (patch) | |
| tree | 6e87c9c5d56cab57a78c2671a69d4d1224260b50 /src/southbridge/intel/bd82x6x | |
| parent | 95932ba9b7bb1ad1f81cb4a5d16b9fd9c203b254 (diff) | |
sb/intel/common: Fix GPE0 related register conflict
When ACPI GPE0 block was extended to 64 events or 8 bytes,
ACPI PM register space was slightly modified. After
adjustment, PM2_CNT register moved to 0x50 where register
SS_CNT was previously defined to be.
For platforms that have a valid use for PM2_CNT==0x50 in
their FADT, remove overlapping definition of SS_CNT.
On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status()
incorrectly addressed also GPE0_EN register. For a bit cleaner
implementation, define GPE0_HAS_64_EVENTS.
Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 34b36c3866..2ebec62300 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -428,7 +428,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -462,8 +461,9 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 +#define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 + #define TCO1_STS 0x64 #define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) |