diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-04-23 13:52:54 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-04-28 16:46:00 +0000 |
| commit | 5b574e1c859a095ecdf2728a1a6db2d854bbb668 (patch) | |
| tree | bfe8e0d52cbd2b1fc8f41d2e8935a97391f3889e /src/southbridge/intel/bd82x6x | |
| parent | c486c78020fc426d8ddb2a74fac5f7c402e4af29 (diff) | |
mb/google/deltaur: Change H1 I2C speed to STANDARD
Currently, Deltaur’s I2C speed has not been tuned yet, so slow down
the H1 I2C to avoid I2C error for short term.
Error logs:
Reading cr50 TPM mode
I2C receive timeout
I2C read failed: bus 3 addr 0x50
BUG=b:154310066
TEST=Check H1 has no I2C error occurring and can be updated by gsctool.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
0 files changed, 0 insertions, 0 deletions