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authorMartin Roth <martin@coreboot.org>2021-10-01 14:53:22 -0600
committerMartin Roth <martinroth@google.com>2021-10-05 18:07:08 +0000
commit26f97f9532933da3c1d72a7918c8a24457bbc1c0 (patch)
tree8c25279e58ef541fae197ec193f5642a9b21b2d4 /src/southbridge/intel/bd82x6x
parent50863daef8ed75c0cb3dfd375e7622c898de5821 (diff)
src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/azalia.c2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 1f14c422a8..3b07a15298 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -162,7 +162,7 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index b4f0c4c5fc..dfebaf0dac 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -31,7 +31,7 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/