diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-12-29 05:12:56 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-20 09:22:59 +0000 |
| commit | c196246f75ae8fd235055250593fc7a78f5f3888 (patch) | |
| tree | bbb1cfa12daf81da3798d27649123ae80369a142 /src/southbridge/intel/bd82x6x | |
| parent | e1383d39d794278b6e88b1658c620ad016bef05d (diff) | |
ACPI GNVS: Drop most dev_count_cpu()
Only amd/picasso and amd/stoneyridge have reference to
PCNT and that could be replaced with acpigen.
Remove the PCNT name from GNVS OperationRegion elsewhere.
Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/include/soc/nvs.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 1 |
3 files changed, 2 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 9194f3f5ce..c6c7397031 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -58,7 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state - PCNT, 8, // 0x2d - Processor count + , 8, // 0x2d - Processor count /* Super I/O & CMOS config */ Offset (0x32), NATP, 8, // 0x32 - diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h index bbfa4c8d21..25e5b6edac 100644 --- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h +++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h @@ -49,7 +49,7 @@ struct __packed global_nvs { u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ + u8 unused_was_pcnt; /* 0x2d - Processor Count */ u8 rsvd4[4]; /* Super I/O & CMOS config */ u8 natp; /* 0x32 - SIO type */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c2e7a86f09..a351bc3900 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -645,7 +645,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); } static const char *lpc_acpi_name(const struct device *dev) |