diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:40:21 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 16:29:35 +0000 |
| commit | 131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef (patch) | |
| tree | accfc86126dba3bf22fe731689ee791894a3bcaa /src/southbridge/intel/bd82x6x | |
| parent | b69bbfe1ef52421f0bbe1e632d99dc264660ee02 (diff) | |
src/southbridge: Drop unneeded empty lines
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/fadt.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smihandler.c | 1 |
5 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 1d132ee7ea..6320d2ea9f 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -202,7 +202,6 @@ int intel_early_me_init_done(u8 status) timestamp_add_now(TS_ME_INFORM_DRAM_DONE); } - me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); @@ -220,7 +219,6 @@ int intel_early_me_init_done(u8 status) printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); - /* Return the requested BIOS action */ printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", me_ack_values[(hfs & 0xe) >> 1]); diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index ffd7db3f03..b0f4777d03 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->sci_int = 0x9; if (permanent_smi_handler()) { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 2407d92dc1..df5625afa5 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -734,7 +734,6 @@ static struct device_operations device_ops = { .ops_pci = &pci_dev_ops_pci, }; - /* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and * Intel C200 Series Chipset */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 5aaf661041..c26078ff6c 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -197,7 +197,6 @@ struct me_fw_version { u16 recovery_hot_fix; } __packed; - #define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 7211da37a9..40672f87cd 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -142,7 +142,6 @@ void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 2)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) |