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authorStefan Reinauer <reinauer@chromium.org>2012-06-13 16:31:50 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-24 23:28:47 +0200
commit9842ad8ac5256d1800490c392b8cf7e4edd21ddc (patch)
treec02edc09929d95b2d42a673ada11b8700a764798 /src/southbridge/intel/bd82x6x
parenta306ad701e88089749deba9f1e48ed6e05bca5cc (diff)
Fix automatic ME detection in finalize
The ME needs to be talked to through the PCIe memory mapped config space. Change-Id: Ic2c5a572a126722a08a82d95df13d11507586c6b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1284 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/me.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 0c40ab4276..25b88b98bb 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -533,7 +533,7 @@ static void intel_me7_finalize_smm(void)
void intel_me_finalize_smm(void)
{
- u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
+ u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
switch (did) {
case 0x80861c3a:
intel_me7_finalize_smm();